Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors

Abstract

The use of bitand digit-serial arrays in digital designs is attractive, because of the large savings in chip area that are possible with such designs as well as the comparative ease with which such designs can be conceived and fabricated. These arrays are used extensively in digital signal processing applications and are part of circuits generated by silicon compilers. A number of bitand digit-serial architectures have been proposed by Jasica et al. [l], Scanlon and Fuchs [2], Kanopoulos [3], Lyon [4], Denyer and Renshaw [5], and Hartley and Corbett [6]. Test generation for such arrays is a difficult problem due to the presence of internal system states that are neither directly controllable nor observable. The erroneous system states can mask errors activated by a test sequence unless the test sequence is carefully designed for the bitand digit-serial array to be tested. Breuer [7] studied the problem of fault detection in linear cascades of identical machines. He derived strong necessary and sufficient conditions for such cascades to be testable by two or three uniform (preset) experiments. Test sequences for two bit-serial multipliers are presented by Davis et al. [8]. An ad hoc procedure based on exhaustive simulation of all faulty truth tables of a full adder