Efficient pipelined multi-operand adders with high throughput and low latency: designs and applications

Abstract

We describe several approaches for performing multi-operand addition. Our constructions are regular and modularized, and their required circuit size and depth compare favorably with previously proposed schemes. We show that the sum of n k-bit integers can be found using pipelined circuits of size nk/d+O(k(logn+logk)), latency O(logn+logk+d), and a feedback loop with a single full-adder delay, where d can be any positive integer. We also develop several techniques to fine-tune the constructions in order to obtain circuits that are adaptive to application requirements. In particular we generalize the block-save technique and obtain competitive constructions for multi-operand addition by combining the technique with that of ripple adder trees. We also demonstrate how to apply multi-operand adders to the computation of several useful functions.