Abstract
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO<sub>2</sub> field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL) current in erase operation of FeFETs with a floating body. We also introduced a novel gate stack process for low voltage operation by inserting a Ti layer in the metal gate. The Ti layer insertion can suppress the growth of an interfacial layer (IL) by controlling oxygen intrusion into the IL during the rapid thermal anneal (RTA) process. We demonstrated an efficient erase operation at shorter and lower pulse voltage with GIDL current in the overlap structure than in the underlap structure. A compact FeFET retention model is developed based on the surface-potential based FET model, the nucleation-limited-switching (NLS) model, and the retention model of ferroelectric (FE) capacitor. Faster degradation of the program state observed in the experiment can be explained by electron detrapping according to the modeling and simulation.
Highlights
The Recent advancement of Internet-of-Things (IoT) technologies with big data makes the data traffic between IoT edge devices and cloud servers heavier than ever seen
The generation of minority-carrier holes is important to fix the body potential, apply large voltage in the gate oxide, and balance with large ferroelectric polarization charge. 3D vertical NAND flash memories utilize GIDL current generated by the access transistor to supply minority-carrier holes for the efficient erase operation [3,4,5]
We explored the role of GIDL current in SOI junctionless field effect transistors (FeFETs) for erase operation by TCAD simulation with a GIDL current model [19]
Summary
The Recent advancement of Internet-of-Things (IoT) technologies with big data makes the data traffic between IoT edge devices and cloud servers heavier than ever seen. 3D vertical NAND flash memories utilize GIDL current generated by the access transistor to supply minority-carrier holes for the efficient erase operation [3,4,5]. There are relevant reports for inversion-mode FeFETs [6,7], it has not been fully studied for junctionless FeFET, yet Another challenge of HfO2-based FeFET is the low-k interfacial layer (IL) growth during rapid thermal annealing (RTA) process, which causes large voltage drop on the IL, divides gate voltage, prevents low-voltage operation, and leads to reliability problems. One possible solution is to insert oxygen scavenging material such as Ti to suppress the growth of the IL in the metal/HfO2/Si gate stack during high temperature RTA process as reported [8]. This paper is an extended version of the previous conference proceedings [18] by adding detail descriptions of the technical contents, physical analysis, and electrical characterization
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