Efficient Concurrent Error Detection for SEC-DAEC Encoders

Abstract

In the last decade, a number of Single Error Correction Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to protect memories against Multiple Cell Upsets (MCUs). These codes are able to correct errors that affect two adjacent bits that is one of the most common MCU patterns. However, soft errors can also affect the encoder and decoder circuitry creating data corruption. An alternative to protect the encoders is to use parity prediction Concurrent Error Detection (CED) to detect errors and avoid writing erroneous words in the memory. This approach has been previously studied for Orthogonal Latin Square (OLS) codes and for matrix codes. In this paper, the implementation of parity prediction Concurrent Error Detection (CED) for SEC-DAEC codes is considered. To that end, first it is shown that CED has a significant cost for the existing SEC-DAEC codes. This is because they are odd weight codes and parity prediction is much simpler for even weight codes. Based on that observation, even weight SEC-DAEC codes are designed and evaluated. The results show that CED can be efficiently implemented in the proposed codes that achieve a significant reduction in encoder circuit complexity compared to previously proposed SEC-DAEC codes.