Abstract

The full integration of DC-DC converters offers great promise for dramatic reduction in power consumption and the number of board-level components in complex systems on chip. Some papers compare the numerous published on-chip and on-die converter structures, but there is the need for an approach to accurately compare the main basic DC-DC conversion topologies. Therefore, this paper presents a method to compare the efficiencies of CMOS integrated capacitive-, inductive- and resonant-based switching converters. The loss mechanism of each structure in hard-switching conditions is detailed and the analytical equations of the power loss and output voltage are given as a function of few CMOS technology parameters. The resulting models can be used to accurately predict converter efficiency in the early design phase, to compare the basic structure in particular the technology node or to orient the passive choice. The proposed method is then applied to design, optimize and compare fully-integrated power delivery requirements on a $1~{\hbox {mm}}^{2}$ on-die area in 65 nm CMOS technology over three decades of power density. The results also underline the high efficiency of the promising resonant-based converter.

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