Effective screening for NBTI effect on SRAM-based memory

Abstract

Reliability of metal-oxide-semiconductor field-effect-transistor (MOSFET) devices is a growing concern as the scaling of these devices is increased. Major contributors to the reliability issues of MOSFET devices include negative bias temperature instability (NBTI) in p-type MOSFET. NBTI phenomena causes threshold voltage shift (increasing Vt) of pMOS devices over time. This results in slow down of devices and loss of performance for logic gates. Vt shift of pMOS due to NBTI compromises SRAM stability and could cause corruption of stored data due to negative effects on Static Noise margin (SNM). It is essential to screen for NBTI effect at production time to eliminate future field failures. Current methods to screen for NBTI are expensive and inconclusive. We propose a design for test approach which enables screening for NBTI with low overhead and less test time.