Abstract
Due to the continuous rising demand of handheld devices like iPods, mobile, tablets; specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.
Highlights
With continuous scaling of the supply voltages, the SRAM cell does not function properly at sub-threshold supply voltage ranges as at theses voltages the Static Noise Margin (SNM) deteriorates and is not enough for reliable and stable operation
In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current
In order to verify the robustness of an integrated circuit design, semiconductor manufacturers will fabricate corner lots, which are groups of wafers that have had process parameters adjusted according to these extremes, and will test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination in a process called characterization
Summary
With continuous scaling of the supply voltages, the SRAM cell does not function properly at sub-threshold supply voltage ranges as at theses voltages the SNM deteriorates and is not enough for reliable and stable operation. With the increased complexity of the microprocessors and digital signal processors on-chip register files and SRAMs are expected to increase significantly while maintaining the stability. Various SRAMs from 6T to 13T [2,3,4,5] has been proposed to improve the stability and performance along with low power consumption. In this paper we have analyzed the stability and leakage of our proposed SRAM PNN stack at various process corners. This cell is suitable and operational for deep sub-threshold technology and is operational at all the process corners. Process variation like dopant variation, temperature, and threshold affects the overall performance of the design at deep sub micron technology [6].
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