Abstract
The Noise estimation and avoidance are becoming critical, in today’s high performance IC design. An accurate yet efficient crosstalk noise model which contains as many driver/interconnect parameters as possible, is necessary for any sensitivity based noise avoidance approach. In this paper, we present an analysis for crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. Also shown that crosstalk can be minimized by driver sizing optimization technique. These models are verified for various deep submicron technologies.
Highlights
Coupling capacitance between neighboring nets is a dominant component in today’s deep submicron designs as taller and narrower lines are being laid out closer to each other [1]
To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages
In [6], telegraph equations are solved directly to find a set of analytical formulae for peak noise in capacitively coupled bus lines. [7] derives bounds for crosstalk noise using a lumped model but assuming a step input for aggressor driver
Summary
Coupling capacitance between neighboring nets is a dominant component in today’s deep submicron designs as taller and narrower lines are being laid out closer to each other [1]. Any such tool requires fast yet accurate crosstalk noise models both to estimate noise and to see the effects of various interconnect and driver parameters on noise. This assumption causes the model to significantly overestimate peak noise, especially for small aggressor slews, which is very likely to occur in today’s deep submicron designs.
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