Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in $5~\mu$ s

Abstract

A 16 Gb/s 1-tap Infinite impulse response (IIR) + 1-tap discrete-time (DT) decision feedback equalizer (DFE) with integrated clock recovery and adaptation is demonstrated in 28 nm FD-SOI CMOS. Using a CMOS phase rotator, 0.7 unit interval (UI) high-frequency jitter tolerance is achieved when operating mesochronously, and over 0.4 UI operating plesiochronously. The half-rate architecture includes a novel 2:1 multiplexer to reduce delay in the IIR feedback path. With a 28 dB loss channel, a BER below $10^{-12}$ is measured over a 0.32 UI timing window with a TX swing of 0.8 Vpp-diff. Using a 2 Vpp-diff TX swing, a 30 dB loss channel has a measured BER below $10^{-12}$ over a 0.3 UI timing window. A novel edge-based algorithm adapts both IIR and DT equalizer coefficients using the same high-speed circuitry and signals required for clock recovery. The algorithm utilizes all transitions to inform the adaptation of all equalizer coefficients, thereby providing faster convergence than previously-reported algorithms which await specific patterns. Moreover, the adaptation freezes automatically unless a diverse set of data patterns is received, thereby making the algorithm robust in the presence of poorly-conditioned data. The adaptive DFE converges within $5~\mu \text{s}$ .