Dynamic multi-level simulation of digital hardware designs

Abstract

This paper presents the issue of dynamic multi-level simulation of hardware designs that addresses the problem of inefficiency associated with the conventional static multi-level simulation ap proaches as in ADLIB-SABLE (Hill 1980), DIANA (Demou and Arnout 1979), and SPLICE (Newton 1978). In this approach, digital sim ulation or verification (McWilliams 1980) of hardware designs is initiated at a high level of abstraction. When detailed results are required for one or more high-level components or for tracing the source of an error to any of the lower-level devices, the appropriate components are expanded into their lower-level implementations. Then simulation or verification initiates at that level. Following completion of execution at the lower level, con trol returns to the higher level. Consequently, only those sub parts of a digital design are selected for expansion and detailed simulation that are dynamically warranted by the higher-level simulation results. Unnecessary simulation effort may be elimi nated. Dynamic multi-level simulation or zooming is a generaliza tion of the swapping technique (Szygenda 1973) to functional and fault simulation and timing verification and to the differ ent abstraction levels in the hierarchy between the gate- and behavior-levels. This paper also addresses the implementation of zooming in the rule-based design verifier, RDV (Ghosh 1984), at Stanford University. That RDV uses Ada (U.S. Dept. of Defense 1983) as a hardware description language and simulation envi ronment (Ghosh 1985).