Dynamic current reference technique for enhanced transient response in current-feedback low-dropout regulators

In this work, a novel voltage sensorless Direct Power Control (DPC) approach of Active Front End (AFE) rectifier based on virtual flux and dc-link dynamic reference design technique is presented. Firstly, the PI controller is eliminated from the outer dc-link voltage control loop with the application of dynamic dc-link reference design technique and line voltage sensors by using virtual flux technique. Further, a simple way to obtain the dc-link voltage based on the switching states of the rectifier is implemented to remove the outer loop voltage sensor also and hence the voltage sensorless DPC approach has achieved. Finally, the Experimental results of both the approaches, one with dc-link voltage sensor but without PI controller and another with the absence of both PI controller and dc-link voltage sensor is presented. Numerical experimental results depict the better control from the proposed techniques regarding reduction in active, reactive power ripple and THD in the line current.

The implementation of multistep direct model predictive control (MPC) for dc–dc boost converters overcomes the well-known issue of nonminimum phase behavior. However, it can lead to a high computational burden depending on the prediction horizon length. In this paper, a simple and computationally efficient MPC method for dc–dc boost converters is proposed. The key novelty of the presented control strategy lies in the way dynamic references are handled. The control strategy is capable of providing suitable references for the inductor current and the output voltage, without requiring additional control loops. Moreover, this reference design allows the predictive controller to be implemented with a single-step prediction horizon. Thus, a significant reduction in the required real-time calculations executed in the control hardware is achieved. To obtain constant switching frequency, the power switch commutation instants within a sampling period are considered as control inputs. Therefore, the predictive controller is formulated as a continuous control set MPC. Additionally, the proposed formulation is able to deal with different operation modes of the converter without changing the controller structure. Finally, an observer is used to dynamically modify the reference to provide robustness to system parameter uncertainties. Simulation and experimental results show an accurate tracking of dynamic inductor current and output voltage references, while respecting the restrictions on maximum inductor current levels of the converter.

This paper presents a fast transient low-dropout regulator (LDO) with bulk modulation technique and dynamic transient boost circuit (TBC) for system-on-chip (SoC) applications. The conventional bulk modulation and dynamic biasing techniques failed to obtain low quiescent current and better stability at no-load conditions. The proposed bulk modulation technique implemented by using only one error amplifier with two different gain stages to achieve the small quiescent current and to obtain good regulation with better driving capability. The proposed TBC combines the dynamic biasing and output compensation techniques to enhance the transient response of LDO drastically. The proposed design is simulated in the 40nm LVT CMOS process shows that the LDO delivers 1V output voltage and consumes 15μA of quiescent current with the supply voltage of 1.1V. When the load current changes from 100nA to 10mA with a large slew rate of 200ps, undershoot and settling time are 450mV and 8ns respectively. Compared to LDO without TBC, the proposed LDO offers good stability, better driving capability, ∼10× less undershoot and ∼10× fast settling time.

Ultra low power capless LDO with dynamic biasing of derivative feedback

A dual-voltage-loop digital control architecture with non-linear control algorithm is proposed in this paper. An adaptive voltage positioning (AVP) control unit was generalized to achieve adaptive voltage positioning, by generating dynamic voltage reference and dynamic current reference. A dynamic reference step adjustment method lowers the high speed requirement of reference updating clock; a non-linear control minimizes the transient-assertion-to-action delay and maximizes the inductor current slew rate; and a transient detection circuit recognizes the load transient state in a manner adaptive to the amount and slew rate of load current transient. Theoretical, simulation and experimental results prove the effective operation and excellent dynamic performance of the digital controller.

This paper presents an output capacitor-less, NMOS regulation FET low-dropout regulator (LDO) with fast load transient response in 55 nm CMOS process. The LDO employs a push-pull error amplifier to achieve high slew rate at low quiescent current and a bidirectional dynamic biasing technique to further improve the load transient response, with barely extra quiescent current. The error amplifier includes a common-gate input stage, whose low input resistance improves stability of the LDO over a wide range of load currents. Due to the low output impedance, NMOS regulation FET is used to improve the transient response. The simulated results show that the LDO with a power supply range from 2.5 to 3.6 V achieves a stable 1.2 V output. When the load current changes in the range of 200 μA - 10 mA with a rise time and a fall time of 200 ns, the LDO can settle within 2.7 μs under a quiescent current of 123 nA.

This article presents a model predictive sliding control (MPSC) strategy with the dynamic reference tracking for cascaded H-bridge (CHB) multilevel converters. The nonlinear predicted sliding mode control (PSMC) and linear model predictive control (MPC) are combined as a two-level cascaded control structure. The proposed approach aims to get rid of time-consuming tuning to reach the good performance in the presence of uncertainties and disturbances, such as proportional–integral (PI). The MPC scheme is designed to predict the future optimal current and voltage vectors with a designed cost function. The high-level PSMC algorithm is proposed for the dynamic current reference with less chattering problems. The stability of the proposed strategy is analyzed with the Lyapunov direct method. The design principle of the system parameters is introduced with a step-by-step tuning procedure. With the proposed method, the response time can be reduced from 60 to 30 ms during the start-up conditions in the simulation tests. The overshoot of the cell voltages can be eliminated with low-harmonics current and dc-link voltage targets tracking. The validity and effectiveness of the proposed method are implemented by the experimental tests on a laboratory two-cell CHB converter. Compared with the PI-based MPC approach, the current total harmonic distortion (THD) can be reduced and the dc-side performance, including overshoot/undershoot and response speed, can be improved.

The external capacitors of conventional LDO (Low Drop Out) regulator have a function to improve the transient response characteristics affected by the overshoot and undershoot. However, the LDO regulator proposed in this study is replaced the function of the external output capacitor with a dual push-pull stage and is achieved a fast transient response by a newly added control path to replace the function of the capacitor removed along with the existing feedback path. The proposed LDO regulator can also be provided the improved ESD (Electro Static Discharge) robustness characteristics by applying the SCR (Silicon Control Rectifier)-based ESD (Electro Static Discharge) protection device embedded into the output node and power line. The LDO regulator with dual push-pull circuit proposed in this study was operated at a maximum load current of 100 mA, an output voltage of 3 V, and an input voltage range of 3.3 ~ 4.5 V. As a result of the measurement, an undershoot voltage of 110 mV and an overshoot voltage of 123 mV were maintained when a load current of 100 mA was applied. Further, the ESD robustness characteristic of HBM is guaranteed at 8kV or higher.

A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique

A flipped voltage follower structure based on a dynamic current boosting technique is proposed which enables the fast-transient behavior. It is applied to an output capacitor-less low-dropout (LDO) regulator to improve the output transient response and reduce the over/undershoots of the output voltage when the load current or the input voltage is suddenly changed. The proposed low-dropout regulator is simulated in 0.18 μm CMOS technology, which the output voltage is regulated at 1 V with a dropout voltage of about 114 mV. The output voltage over/undershoot amplitudes of the proposed LDO are obtained in 99.52/551.8 mV with the settling time of fewer than 1.3 μs for the load current changes from 0.1 to 100 mA with 200 ns rise/fall times.

The Theme is that of the ‘bandgap voltage reference principle’, The Variations are some unusual and hitherto unpublished derivatives of the form. Most are of moderate to high accuracy, and generally intended for operation in a low-voltage commercial context, which typically means a minimum supply of 2.7V and a minimum temperature of-30°C. In some cases, the supply may be as low as 1.2V and operation may be required at temperatures of-55°C, though rarely in combination. A few are very simple, and useful where accuracy is needed only over a narrow supply range. The emphasis throughout is on allbipolar, and in many cases, all-NPN, realizations, while acknowledging that complementary bipolar and BiCMOS processes often provide implementation advantages. Brief mention will be made of the special challenges of realizing voltage References in an all-CMOS process; a dynamic reference, interesting and valuable because it requires only a single junction device, is described.

Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor

A Nested Miller Compensation with a large feed-forward transconductor for capacitor-less flipped voltage follower low dropout regulator

This paper presents an integrated current-sensing system (CSS) that is intended for the use in battery-powered devices. It consists of a $10\,\hbox{m}{\Omega} $ on-chip metal shunt resistor, a switched-capacitor (SC) $\Delta \Sigma $ ADC, and a dynamic bandgap reference (BGR) that provides the ADC’s reference voltage and also senses the shunt’s temperature. The CSS is realized in a standard $0.13\,\mu \text{m}$ CMOS process, occupies $1.15\,\text{mm}^2$ and draws $55\,\mu \text{A}$ from a 1.5 V supply. Extensive measurements were made on 24 devices, 12 of which were directly bonded to a printed-circuit board (PCB) and 12 of which were packaged in a standard HVQFN plastic package. For currents ranging from $-5 $ to $+ 5$ A and over a temperature range of $- 55^{\;\circ} {\text{C}}$ to $+ 85^{\;\circ} {\text{C}}$ , they exhibit a maximum offset of $16\;\mu \text{A}$ and a maximum gain error of $\pm 0.3\% $ . This level of accuracy represents a significant improvement on the state of the art, and was achieved by the use of an accurate shunt temperature compensation scheme, a low-leakage sampling scheme, and several dynamic error correction techniques.

This paper presents a micropower current-sensing system (CSS) for battery monitoring, which consists of a calibrated shunt resistor, a ΔΣ ADC, and a dynamic bandgap reference (BGR). For currents ranging from 0 to 1A over the industrial temperature range (-40°C to +85°C), it exhibits 10μA offset and ±0.03% (3σ) gain error, which is a 3× improvement on systems with off-chip external references [1,2]. This level of accuracy is achieved by the use of dynamic error-correction techniques, digital temperature compensation, and an on-chip dynamic BGR, whose spread is corrected by a single room-temperature trim.