Abstract
The design of a novel dynamic content addressable memory (CAM) cell suitable for high-density arrays is described. The proposed cell is capable of storing three internal states: ONE, ZERO, and `don't care' (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in nondestructive current-driven READ and MATCH operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2-/spl mu/m design rules, buried contacts, single-level metal, and low-resistance polycide lines results in a CAM cell area of 25/spl times/22 /spl mu/m/SUP 2/, which is comparable to 64-kb static random access memory (RAM) cell areas. The CAM cell was successfully fabricated using a 4-/spl mu/m NMOS process and its operation was verified with a 2/spl times/3-bit array.
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