Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Presented is a circuit technique that mitigates the impact of single-event transient (SET) in deep submicrometer circuits with minimal speed, power, and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and the skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate SETs with the polarity of $1\rightarrow 0$ and $0\rightarrow 1$, respectively. We study inverter chain circuits as well as sum-of-products implementation of random logic circuits in a typical 0.18-$\mu{\hbox {m}}$ process under the influence of radiation induced soft errors. We quantify the SET tolerance of the proposed technique by using an error map and a recently developed tool soft-error rate analyzer (SERA). The results show that the DSFF incurs no speed penalty, if no SETs have reached the input of DSFF. Otherwise, the DSFF alone eliminates the $1\rightarrow 0$ SETs while incurring a worst case speed and power penalty of 310 ps and 39 $\mu \hbox {W} $, respectively. The SCMOS eliminates the $0\rightarrow 1$ SETs when the skewing factor is greater than four. Thus, the proposed technique potentially eliminates the impact of SETs with both polarities. </para>