Abstract
In this work, a hardware accelerator has been developed for a RISC-V processor. The ‘Parashu’ Shakti processor is the SoC of choice for application testing and development. The IP is designed to speed up applications involving dual quaternion operations. Our module primarily aids dual quaternion multiplication which further helps with other complex operations like translation, rotation and transformation. Two solutions have been proposed for the same, i.e. either a quaternion IP if power and resource utilization is a concern, or a dual quaternion IP if performance gain is the primary objective. The latter is however at the expense of relatively more resource utilization. The former IP takes longer execution time to perform the same task but is more versatile since it can be used in applications involving both quaternion and dual quaternion operations.
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