Abstract
This paper presents a dual-core floating-point FFT processor. The internal butterfly unit of the processor based on CORDIC algorithm, and uses an iterative computation process instead of two computation process which is the complex multiplication and the evaluation of trigonometric function. The butterfly unit has nothing to do with the external memory size, so it can handle large quantities of data. Based on this unit, the processor uses two logical processing core and pipeline system to improve the throughput and instantaneity. So the design has large scope of input and high-precision operation features. Finally, we make a timing simulation for the Alteras chip of EP2C20F484C6, which can run correctly under the 100MHz system clock.
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