Dr. Sugako Otani: Pioneering processor architect [Women to Watch

Performance analysis has always been considered important in computer design work. The area of central processing unit (CPU) design is no exception, where the successful development of performance evaluation tools provides valuable information in the analysis of design tradeoffs. Increasing integration of hardware is producing more complicated processor modules which add to the number of alternatives and decisions to be made in the design process. It is important that these modules work together as a balanced unit with no hidden bottlenecks. This paper describes a project to develop performance simulation as an analysis tool in CPU design. The methodology is first detailed as a three part process in which a performance simulation program is realized that executes an instruction trace using command file directions. Discussion follows on the software implemented, applications of this tool in CPU design, and future goals.

Performance analysis has always been considered important in computer design work. The area of central processing unit (CPU) design is no exception, where the successful development of performance evaluation tools provides valuable information in the analysis of design tradeoffs. Increasing integration of hardware is producing more complicated processor modules which add to the number of alternatives and decisions to be made in the design process. It is important that these modules work together as a balanced unit with no hidden bottlenecks. This paper describes a project to develop performance simulation as an analysis tool in CPU design. The methodology is first detailed as a three part process in which a performance simulation program is realized that executes an instruction trace using command file directions. Discussion follows on the software implemented, applications of this tool in CPU design, and future goals.

This paper presents the design of a high performance AES processor. An optimized AES algorithm without sacrificing its security features is used to design the processor. The proposed design is secured against all kinds of attacks. The design of the processor is simulated on the FPGA platform. Simulation results ensure its proper functionality. Due to a number of unique design consideration, the processor outperforms all other existing solutions in terms of latency which is an important factor for real time operation. The speed performance of the processor is also analyzed and compared with that of other researchers in ASIC technology which also proves its superiority over them.

Designing a central processing unit (CPU) requires intensive manual work of talented experts to implement the circuit logic from design specifications. Although considerable progress has been made in electronic design automation (EDA) to relieve human efforts, all existing EDA tools require hand-crafted formal program codes (e.g., Verilog, Chisel, or C) as the input. To automate the CPU design without human programming, we are motivated to learn the CPU design from only input-output (IO) examples. The key challenge is that the learned CPU design should have almost zero tolerance for inaccuracy, which makes well-known approximate algorithms such as neural networks ineffective. We propose a new AI approach to generate the CPU design in the form of a large-scale Boolean function, from only external IO examples instead of formal program code. This approach employs a novel graph structure called Binary Speculative Diagram (BSD) to approximate the CPU-scale Boolean function accurately. We propose an efficient BSD expansion method based on Boolean Distance, a new metric to quantitatively measure the structural similarity between Boolean functions, gradually increasing the design accuracy up to 100%. Our approach generates an industrial-scale RISC-V CPU design within 5 hours, reducing the design cycle by about 1000x without human involvement. The taped-out chip, Enlightenment-1, the world's first CPU designed by AI, successfully runs the Linux operating system and performs comparably against the human-design Intel 80486SX CPU. Our approach even autonomously discovers human knowledge of the von Neumann architecture.

A design approach for video signal processors is presented that is driven by characteristics of the algorithms, rather than by technological enhancements to conventional microprocessor-style DSP architectures. The goal of this algorithm-driven approach is the design of processors that possess not only the flexibility to execute several algorithms, but an order of magnitude lower complexity than conventional processors. This design approach is applied to the design of a high-speed signal processor targeted at video compression algorithms including the 8/spl times/8 DCT, wavelet/subband coding, and vector quantization. The fabricated processor chip can execute each algorithm at up 25 MPixels/sec and has been implemented with only 80,000 transistors in a 1.2-/spl mu/m CMOS process. >

In the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. Recently, clock speeds have tapered and thermal and power dissipation envelopes have remained flat. However, the demand for increasing performance continues which has fueled the move to integrated multiple processor (multi-core) designs. This paper discusses this trend towards multi-core processor designs, the design challenges that accompany it and a view of the research required to support it

This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor model refinement based on the results of hardware and software simulation and profiling. Thus, traditionally huge teams of hardware and software experts are required to design new programmable architectures. The proposed design flow reduces the design time and enables even non processor experts to overcome the typical design challenges. The presented design methodology is based on a workbench that automates the generation of all required software tools and furthermore closes the gap between high level modeling and hardware implementation via automatic generation of a register transfer level (RTL) model for the target processor. A case study demonstrates the design approach discussing the application specific instruction-set processor (ASIP) design for a fast Fourier transformation (FFT) algorithm. Several processor types such as SIMD and VLIW with various characteristics have been explored to find an optimal processor implementation for this algorithm.

In the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. Recently, clock speeds have tapered and thermal and power dissipation envelopes have remained flat. However, the demand for increasing performance continues which has fueled the move to integrated multiple processor (multi-core) designs. This paper discusses this trend towards multi-core processor designs, the design challenges that accompany it and a view of the research required to support it.

The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper presents processor architecture design, its implementation followed by processor instruction set, data path flow for fetching unit, Register type, I-type and load /store type instruction flow. Thereafter this paper illustrates control unit design of processor that shows the controlling of signals for different units in processor design. Further, a complete internal structure is shown followed by features of novel processor architecture. It has capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.In the end, results have been shown using implementation windows. The complete design has been written using VHDL and then simulated and synthesized by XILINX ISE tool.

Over the next decade, processor design will encounter a number of challenges. The ongoing miniaturization of semiconductor manufacturing technologies that has enabled the integration of hundreds to thousands of processing cores on a single chip is pushing the limits of physical laws. The fabrication process has also grown more complex and globalized with widespread use of third-party IPs (intellectual properties). This development ecosystem has complicated the security and trust view of processors. Some of the pressing processor architecture design questions are: (1) how to use reconfiguration and redundancy to improve reliability without introducing additional and potentially insecure system states, (2) what analytical models lend themselves best to the joint implementation of reliability and security in these systems, and (3) how to optimally and securely share resources and data among processing elements with high degree of reliability. In this work, we present and discuss (1) principal reliability approaches - error correction code, modular redundancy, (2) processor architecture specific reliability, (3) major secure processor architectures. We also highlight key features of a small representative class of the secure and reliable architectures.

For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is introduced by a few advanced CAD vendors. In order to maximize the power reduction of the MMP design, we propose a novel selective sequential clock gating (SeSCG) technique in this paper. The SeSCG scheme can choose optimal sequential clock gating style selectively for ultra-low-power design based on the proposed toggle rate analysis at RT level. We have tested the proposed technique on two real industrial MMP designs using 65 nanometer technology. The experimental results show that the conventional sequential clock gating scheme even increases average 4.77% of total power while the proposed SeSCG technique decreases average 23.71% total power with reasonably very small area overhead (no more than 0.63%) when we use real industrial testbenches for the two industrial MMP designs.

The author briefly looks at trends in microprocessor development and system architecture. A detailed discussion of the system designer's challenges and of how an advanced packaging technology might help is presented. Trends in processor design, trends in system design, and opportunities and challenges for packaging technology are considered. >

The method of power delivery analysis on a network processor and package design is presented. A current profile was developed from the processor design and validated by the measurements. Distributed current sources were used to model the transient current drawn by the silicon. To model the package correctly, distributed circuit elements were used. The sensitivity of the voltage droop to the current stimulus was studied in order to design the appropriate current ramping steps. Two current profiles were studied with measurements to improve the processor design for power integrity.

An Application Specific Instruction Set Processor (ASIP) is widely used as a System on a Chip (SoC) Component. ASIPs possess an instruction set which is tailored to benefit a specific application. Such specialization allows ASIPs to serve as an intermediate between two dominant processor designs styles-ASICs which has high processing abilities at the cost of limited programmability and Programmable solutions such as FPGAs that provide programming flexibility at the cost of less energy efficiency. In this dissertation the goal is to design ASIP, keeping in mind a temperature sensor system. The platform used for processor design is LISA 2.0 description language and processor designing environment from CoWare. CoWare processor designer allows processor architecture to be defined at an abstract level and automatic generation of chain of software tools like assembler, linker and simulator for functional verification followed by RTL level description. RTL level description is used to generate synthesized report of the design using RTL compiler and finally the layout is created using Cadence encounter.

Chip architects from Sun, Cyrix, Motorola, Mips, Intel and Digital see challenges rather than walls in microprocessor design. They share their insights in this virtual roundtable. Tremblay discusses the conflicting goals of improving how much work a processor does per cycle and at the same time shortening the cycle time. Grohoski says we need to reduce the processor complexity to spend less time debugging that complexity. Burgess thinks tightly interwoven designs will better support focused applications. Killian is confident the industry will solve foreseeable problems. He sees "big data" problems as key design drivers. Colwell sees a convergence of factors that make validation a big concern. He foresees future computers as communication enhancement devices. Rubinfeld names five issues as important to processor design and discusses some challenges specific to high-speed processor design. Despite the competitiveness of their field, these six architects shared several insights of interest to those not intimately connected with processor design.