DPL-based novel time equalized CMOS ternary-to-binary converter

Abstract

ABSTRACTRadix-3 (Ternary) logic has been receiving renewed attention as a feasible alternative to conventional Radix-2 system in processor-design and multi-valued logic-design due to computational-ease, speed and reduced interconnect. Yet the real world is binary. Thus to harvest the benefits, the ternary-processing stage must be appended with a ternary-to-binary converter. This work introduces a novel 3-step-strategy to convert Ternary-input into Binary-output. Proposed single-supply, Double-Pass-Transistor-Logic (DPL) Ternary-to-Binary-Converter (TBC) is designed with normal-process Enhancement-type-Metal-Oxide-Semiconductor- Field-Effect-Transistor (E-MOSFET) and wave-pipelined through coarse and fine tuning to achieve faster response with reduced power-dissipation and fabrication-cost/complexity. Data-independent propagation delay in DPL is exploited here to achieve efficient time-equalisation. The TBC is designed, optimised, validated and evaluated on TSMC 180nm Single-Poly-Double-Metal (SPDM) CMOS-process on 1.8V supply-rail at 25°C temperature using Tanner EDA V.13. Ternary values are encoded with 1.8, 0.9 and 0V to represent Ternary-digits (‘trit’s) ‘2’, ‘1’ and ‘0’, respectively. T-Spice post-layout-simulation shows the proposed 2:4 TBC consumes 177.74 μW power operating at 500 Mega-trit-per-second (Mtps) and takes 0.72 ns to convert. To address reliability issue, the corner analysis with TT (Typical), SS (Slow) and FF (Fast) PVT-variation is performed and worst case responses are recorded which are observed to be within acceptable-limit.