Abstract
Double relaxation oscillation SQUID (DROS) combined with an on-chip superconducting digital flux locked-loop (FLL) circuit has been proposed. In this study, we described superconducting digital FLL circuit which consists of an 8-bit up/down counter and an 8-bit R-2R ladder D/A converter. The circuit was designed using 4-Junction Logic (4JL)-gates which are driven by a two phase power supply. In the up/down counter, we employed binary carry lookahead (BCL) circuits for high-speed operation. Logic simulations for the BCL 8-bit up/down counter showed correct operation up to 4 GHz, assuming a 2.5 kA/cm/sup 2/ Nb/Al-AlO/sub x//Nb junction technology. From simulation results high slew rate of 10/sup 7//spl Phi//sub 0//s and dynamic range of 2.5/spl Phi//sub 0/ can be expected.
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