Abstract
Although resistance monitoring write termination (RM-WT) scheme for STT-MRAM can reduce the write energy, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) and intrusion of noise with process variation still seriously deteriorates the stability of the WT operation. In this paper, a double-ended superposition anti-noise write termination (DSA-WT) scheme is proposed and implemented, in which the voltage changes on both BL and SL can be superimposed to boost sensing margin (SM). Schmitt trigger (ST) is adopted to take the place of the inverter (INV) in the traditional WT scheme, which is demonstrated to be helpful for stability improvement. Based on 65-nm CMOS technology, the proposed DSA-WT scheme shows 15% ~33% sensing margin boosting under various PVT conditions and 1000 times lower read bit-error-rate (BER) compared with the other WT schemes. The write done (WD) delay and the energy-delay-product (EDP) achieve 49.6% and 47.2% improvements compared to the state-of-art self-referenced single-ended RM-WT scheme (SS-RM-WT), respectively.
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