Abstract
A poly-Si overpass channel synaptic (OCS) transistor is proposed for the extremely-low-power operation and low RC delay of neuromorphic systems. The OCS transistor has two major structural advantages. First, the on-current ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) can be reduced to sub 100 nA with high on/off ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) because the channel wraps around the fin-shaped bottom gate. Second, the weights of the OCS transistors are finely divided by increasing the volume of the charge storage layer. The inference and weight update operations of a NOR-type OCS array were experimentally demonstrated. It was confirmed that the fabricated diode-connected (D-C) OCS array is suitable for vector-matrix multiplication (VMM) operation with its weighted-sum error smaller than 0.79% in inference. Each synaptic weight in the D-C OCS array was adjusted into sub-nA resolution by Fowler-Nordheim (FN) tunneling with asymmetric gates. Finally, the classification accuracy of the fashion MNIST dataset is 91.29% even after one year with four-bit quantization of spiking neural network (SNN).
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