Abstract
An overview is presented of digital VLSI implementations of artificial neural networks (ANNs) configured as multilayer perceptrons employing the backpropagation learning algorithm. Several other network architectures and learning algorithms are also mentioned for comparison. We focus on those implementations which employ parallel hardware in the learning computations, not simply in the retrieval or classification process. The treatment extends from serial and parallel general-purpose simulators, which are simply programmed to implement these learning algorithms, to full custom CMOS chips or neurocomputers dedicated to one version of the learning model. Among the themes of this paper are topologies, bit-serial communications, arithmetic systems, and trade-offs between flexibility and performance.
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