Abstract
Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs). To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC) in each pixel. An image sensor employing this architecture is designed, built and tested in 0.18 micron complementary metal-oxide-semiconductor (CMOS) technology. It achieves a PSNDR better than state-of-the-art logarithmic sensors and comparable to the human eye. As the approach concerns an array of many ADCs, we use a small-area low-power delta-sigma design. For scalability, each pixel has its own decimator. The prototype is compared to a variety of other image sensors, linear and nonlinear, from industry and academia.
Highlights
With image sensors, dynamic range (DR) is the ratio of largest non-saturating signal to smallest detectable signal
This paper proposes a new architecture for image sensors to tackle the above difficulty
Because signal-to-noise-and-distortion ratio (SNDR) correlates with image quality better than signal-to-noise ratio (SNR), it is preferable to use it for dark limit (DL) and DR estimation
Summary
Dynamic range (DR) is the ratio of largest non-saturating signal to smallest detectable signal. The result is a nonlinear digital pixel sensor (DPS) array, as opposed to the typical active pixel sensor (APS) array, where response to light stimulus is linear and where ADCs are integrated at the column, chip or board level. The potential of this new architecture is demonstrated with experimental results from a prototype, which shows wide DR and high PSNDR at video rates. In another conference proceeding [14], Mahmoodi and Joseph extended the method to design small-area low-power pixel-level ∆Σ ADCs, using patent-pending decimators [15] These methods were presented only with simulated designs of ADCs—there were no sensors and no experiments.
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