Abstract

A new architecture is proposed for digital multiphase modulators that leads to a natural hardware efficient realization without compromise in hardware or performance. The combined modulator, switching phases and output filter are viewed as a digital to analog converter with high power output, or a “power D/A”. The duty cycle command bits are separated into high resolution and low resolution bits, where the low resolution bits directly control the number of converter phases that are on at a given time. Hardware efficiency is achieved by using only a single high resolution block that is time shared among all phases and a simple low resolution block that uses a single counter to track appropriate phasing of the outputs. Relatively little digital logic is required to combine the outputs of the two modules, resulting in an efficient design that scales easily with a large number of phases without requiring significant additional hardware per phase. The duty cycle command is updated at the fast rate of n times the single phase switching frequency, where n is the number of phases. The approach is experimentally verified in a 16 phase system operating at 1.5 MHz per phase with 9 bits (1.3 ns) of PWM resolution.

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