Digital charge-coupled logic (DCCL)

Abstract

A new method of implementing digital logic functions is presented. The method is based on the use of charge-coupled devices in pipeline configurations and results in a very high functional density and an extremely low power dissipation. The authors show how various logic functions such as OR, AND, INVERT, and charge refresh are performed. The operation of a DCCL full-adder is compared with another configuration that uses cascaded dual half-adders and a carry-OR. A floating-gate is required as a binary switch in any function that requires binary inversion such as an exclusive-OR. The switching range of the floating-gate is derived as a function of the gate area, the size of the input charge packet and the extraneous capacitances. The implementation of DCCL pipeline arithmetic is discussed. An 8/spl times/8 multiplier and a 16+16 adder pipeline array now being produced are described. The power dissipation and package density of DCCL are compared with PMOS, NMOS, CMOS, and I/SUP 2/L devices in full-adder configurations and in various size arithmetic arrays. The authors conclude with a description of the present status of the technology and some projections for future uses.