Dielectric and Gate Metal Engineering for Threshold Voltage Modulation in Enhancement Mode Monolayer MoS2 Field Effect Transistors.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as a first-rate candidate for post-silicon channels in field-effect transistors (FETs), particularly in the context of monolithic three-dimensional (M3D) integration. Despite the recent synthetic advances including industry-compatible wafer-scale production, they have predominantly been prepared on the ultra-flat, non-processed surfaces, limiting device architectures to outdated planar FETs and geometrically restricting their versatile applications. Integrating 2D semiconductors into 3D device architectures currently presents two significant challenges: i) stackablity, and ii) scalablility. While 2D material-based FETs have been primarily limited to traditional planar devices structures, their applications to vertically integrated 3D devices have been hindered by low-fidelity transfer method which is certainly challenging in conformally and controllably transferring atomically thin materials onto steep sidewalls. Here, we report a directly growth-and-fabrication approach enabling the dimensional transition from 2D planar FETs to a 3D vertical-channel FETs (VCFETs) through the atomically conformal direct growth of monolayer (ML) MoS2 onto the pre-fabricated VCFET structures (Fig. 1A). Leveraging the inherently anisotropic in-plane growth kinetics and precisely controlled supersaturation based on metal-organic chemical vapor deposition, we achieved 100% step coverage even with sub-1-nm channel thickness without compromised crystallinity along an exceptionally high aspect ratio exceeding 15,000 (Fig. 1B). We proved that monolayer MoS2 grown along the SiO2 vertical sidewall is a single crystal by comparing the angles of the selected-area electron diffraction (SAED) pattern in transmission electron microscope (TEM) at the three vertices of MoS2 (Fig. 1C). Fig. 1D shows a cross-sectional scanning transmission electron microscope (STEM) image of the VCFET with and spatial distribution of each element was also identified by energy dispersive X-ray spectroscopy (EDS) mapping images, and it convincingly suggests that atomically conformal monolayer MoS2 was indeed integrated without discontinuity and void even along a steep trench edge (Fig. 1D). Fig. 1E illustrates the unit device schematic of the monolayer MoS2 VCFET. The experimental and simulated transfer characteristic (I DS-V GS) of VCFET with vertical monolayer MoS2 well-coincide each other, showing the subthreshold swing (SS) of 77mV·dec−1 and the ON/OFF ratio of 108 under a drain-to-source bias (V DS) of 1V (Fig. 1F). Output characteristic (I DS-V DS) indicates the change in conductivity of the MoS2 channel by regulating the V G at steps of 1V from −2V to 5V (Fig. 1G). To evaluate device-to-device variation and statistic distribution of their performance, electrical characterization of the 7×7 VCFETs array was performed and their I DS-V GS curves under V DS = +1V exhibited the excellent reproducibility (Fig. 1H). Fig. 1I shows low OFF-state current density of 10−13A∙μm−1 at all devices in our monolayer MoS2 VCFET array, which is 10 times lower than the International Roadmap for Devices and Systems (IRDS) 2028 low-standby power device requirement (~10−12A∙μm−1). Sentaurus technology computer-aided design (TCAD) simulations for monolayer MoS2 VCFET were performed to investigate the electric field distribution of ON-state (V GS = +5V) and OFF-state (V GS = −2V), respectively (Fig. 1J-K). To demonstrate how electron concentration changes in monolayer MoS2 at the sidewall control the switching operation of the transistor, we fabricated a multi-gate VCFET (Fig. 1L). The additional terminals, a modulation gate (MG) and a back gate (BG), facilitate to form an effective gate length near the control gate (CG), enabling a switching behavior of the transistor. The MG screens the electric field toward the top of the trench from the CG, maintaining the electron concentration of the monolayer MoS2 on the top region of the trench and restricting switching operation to monolayer MoS2 on the vertical sidewall. I DS-V CG curve was obtained by applying the CG bias (V CG) and the BG bias (V BG) of +30V with the floated MG bias (V MG) (Fig. 1M). The fabricated multi-gate VCFET further validated the superior sidewall-gate controllability of the ultrathin monolayer MoS2 channel on the vertical sidewall, with aid of TCAD simulation. In the ON-state (V CG = +2.5V), the MG screens electric field generated by CG, allowing the electric field of CG to accumulate electrons effectively along the vertical monolayer MoS2 sidewall, as shown in Fig. 1N. in the OFF-state (V CG = −2.5V), the electric field contour plot reveals that the electric field from the CG does not reach the top region of trench due the MG, while forming a strong electric field near the CG, leading to deplete the MoS2 channel (Fig. 1O). Our work establishes a tailored pathway for the bespoke monolithic integration of ML semiconductors, positioning them as viable channels for high-density, high-performance computational device. Our integration strategy is undisputed pathway for M3D integration and usher in a new era of atomic-level fabric. Figure 1

A finite Schottky barrier and large contact resistance between monolayer MoS2 and electrodes are the major bottlenecks in developing high-performance field-effect transistors (FETs) that hinder the study of intrinsic quantum behaviors such as valley-spin transport at low temperature. A gate-tunable graphene electrode platform has been developed to improve the performance of MoS2 FETs. However, intrinsic misalignment between the work function of pristine graphene and the conduction band of MoS2 results in a large threshold voltage for the FETs, because of which Ohmic contact behaviors are observed only at very high gate voltages and carrier concentrations (∼1013 cm−2). Here, we present high-performance monolayer MoS2 FETs with Ohmic contact at a modest gate voltage by using a chemical-vapor-deposited (CVD) nitrogen-doped graphene with a high intrinsic electron carrier density. The CVD nitrogen-doped graphene and monolayer MoS2 hybrid FETs platform exhibited a large negative shifted threshold voltage of −54.2 V and barrier-free Ohmic contact under zero gate voltage. Transparent contact by nitrogen-doped graphene led to a 214% enhancement in the on-current and a fourfold improvement in the field-effect carrier mobility of monolayer MoS2 FETs compared with those of a pristine graphene electrode platform. The transport measurements, as well as Raman and X-ray photoelectron spectroscopy analyses before and after thermal annealing, reveal that the atomic C-N bonding in the CVD nitrogen-doped graphene is responsible for the dominant effects of electron doping. Large-scale nitrogen-doped graphene electrodes provide a promising device platform for the development of high-performance devices and the study of unique quantum behaviors.

Two-dimensional MoS2 has emerged as promising material for nanoelectronics and spintronics due to its exotic properties. However, high contact resistance at metal semiconductor MoS2 interface still remains an open issue. Here, we report electronic properties of field effect transistor devices using monolayer MoS2 channels and permalloy (Py) as ferromagnetic (FM) metal contacts. Monolayer MoS2 channels were directly grown on SiO2/Si substrate via chemical vapor deposition technique. The increase in current with back gate voltage (Vg) shows the tunability of FET characteristics. The Schottky barrier height (SBH) estimated for Py/MoS2 contacts is found to be +28.8 meV (at Vg = 0V), which is the smallest value reported so-far for any direct metal (magnetic or non-magnetic)/monolayer MoS2 contact. With the application of positive gate voltage, SBH shows a reduction, which reveals ohmic behavior of Py/MoS2 contacts. Low SBH with controlled ohmic nature of FM contacts is a primary requirement for MoS2 based spintronics and therefore using directly grown MoS2 channels in the present study can pave a path towards high performance devices for large scale applications.

Patterning of transition metal dichalcogenides catalyzed by surface plasmons with atomic precision

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.

Atomic layer deposition (ALD) of high-k dielectric films on MoS2 channels can lead to inadvertent remote electron doping of channels owing to nonequilibrium ALD conditions, such as the low temperatures and short purge times required for pinhole-free coating, as well as the weak physical adsorption of ALD precursors on MoS2. In this study, we propose the application of a simple and effective H2O vapor post-treatment (H2O PT) at 100 °C immediately after complete integration of bottom- and top-gate monolayer MoS2 field-effect transistors (FETs), to address the inadvertent channel doping effect. When H2O PT was applied to bottom-gate monolayer MoS2 FETs with an ALD-Al2O3 passivation layer, the mitigation of channel doping was confirmed through electrical and optical measurements. Chemical analyses indicated that H2O PT alleviated the remote doping effect by reducing the number of C/H impurities and possible oxygen defects near the ALD-Al2O3/MoS2 interface. These impurities and defects were associated with the incomplete reaction of the ALD precursor due to the nonequilibrium ALD used for the complete coating of Al2O3 on MoS2. Applying H2O PT to top-gate monolayer MoS2 FET arrays significantly narrowed the distributions of the threshold voltage and subthreshold swing. Moreover, it reduced the gate dielectric leakage current induced by the dielectric damage incurred during physical vapor deposition of the gate electrode. Finally, the time-dependent stability of top-gate monolayer MoS2 FETs subjected to H2O PT was confirmed for at least two months in air.

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS2 and WS2 films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS2 FETs and 160 WS2 FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm2 chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm2 V−1 s−1 in WS2 FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits.

Defects play a pivotal role in limiting the performance and reliability of nanoscale devices. Field-effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors such as monolayer MoS2 are no exception. Probing defect dynamics in 2D FETs is therefore of significant interest. Here, we present a comprehensive insight into various defect dynamics observed in monolayer MoS2 FETs at varying gate biases and temperatures. The measured source-to-drain currents exhibit random telegraph signals (RTS) owing to the transfer of charges between the semiconducting channel and individual defects. Based on the modeled temperature and gate bias dependence, oxygen vacancies or aluminum interstitials are probable defect candidates. Several types of RTSs are observed including anomalous RTS and giant RTS indicating local current crowding effects and rich defect dynamics in monolayer MoS2 FETs. This study explores defect dynamics in large area-grown monolayer MoS2 with ALD-grown Al2O3 as the gate dielectric.

The negative differential resistance (NDR) effect has been widely investigated for the development of various electronic devices. Apart from traditional semiconductor-based devices, two-dimensional (2D) transition metal dichalcogenide (TMD)-based field-effect transistors (FETs) have also recently exhibited NDR behavior in several of their heterostructures. However, to observe NDR in the form of monolayer MoS2, theoretical prediction has revealed that the material should be more profoundly affected by sulfur (S) vacancy defects. In this work, monolayer MoS2 FETs with a specific amount of S-vacancy defects are fabricated using three approaches, namely chemical treatment (KOH solution), physical treatment (electron beam bombardment), and as-grown MoS2. Based on systematic studies on the correlation of the S-vacancies with both the device's electron transport characteristics and spectroscopic analysis, the NDR has been clearly observed in the defect-engineered monolayer MoS2 FETs with an S-vacancy (VS) amount of ∼5 ± 0.5%. Consequently, stable NDR behavior can be observed at room temperature, and its peak-to-valley ratio can also be effectively modulated via the gate electric field and light intensity. Through these results, it is envisioned that more electronic applications based on defect-engineered layered TMDs will emerge in the near future.

We investigate the impact of different substrates on the performance of a monolayer MoS2 field-effect transistor (FET) by calculating the interface charge density between the MoS2 layer and the substrate using first-principle calculations based on density functional theory to provide details about the overlap of electron orbitals at the interface. The electrical characteristics of the monolayer MoS2 FET are determined by using the extracted interface charge density in numerical simulations. The electron transport behavior of the monolayer MoS2 FET is modeled using the nonequilibrium Green’s function with mode space (NEGF_MS) approach. We study and compare the performance of monolayer MoS2 FETs on different substrates, viz. SiO2, HfSiO4, Si3N4, HfO2, and h-BN. The results reveal that the monolayer MoS2 FET on the h-BN/Si substrate exhibits an on-current of 548 µA/µm and a subthreshold swing of 65 mV/dec.

We report effective and stable electron doping of monolayer molybdenum disulfide (MoS2) by cesium carbonate (Cs2CO3) surface functionalization. The electron charge carrier concentration in exfoliated monolayer MoS2 can be increased by about 9 times after Cs2CO3 functionalization. The n-type doping effect was evaluated by in situ transport measurements of MoS2 field-effect transistors (FETs) and further corroborated by in situ ultraviolet photoelectron spectroscopy, X-ray photoelectron spectroscopy, and Raman scattering measurements. The electron doping enhances the formation of negative trions (i.e., a quasiparticle comprising two electrons and one hole) in monolayer MoS2 under light irradiation and significantly reduces the charge recombination of photoexcited electron-hole pairs. This results in large photoluminescence suppression and an obvious photocurrent enhancement in monolayer MoS2 FETs.

Owing to its promising electronic application of monolayer (ML) MoS2, ML MoS2–metal contacts have been widely explored. The experiments reveal a very strong Fermi level pinning, and the corresponding pinning factor is about 0.1 [Nature 2018, 557, 696–700], but all the existing calculations give a larger pinning factor of about 0.3. Such an apparent discrepancy is attributed to the defects in samples. In this paper, the Schottky barriers are reexamined in the pristine ML MoS2 field-effect transistors (FETs) with a series of metal electrodes (Au, Pt, Ag, Ti, Cr, Pd, Ni, and ML CCr2) by using ab initio quantum transport simulation. The Schottky barrier heights obtained from our ab initio quantum transport simulation are in better agreement with those observed in experiments for Au and Pt electrodes, and the calculated pinning factor is also improved. Our work highlights the importance of the inclusion of the coupling between the electrode and channel in determining the pinning behavior. Hence, ab initio quantum transport simulation is an improved method to determine the SBH and the pinning factor in low-dimensional semiconductor FETs.

Field‐effect transistors (FETs) fabricated with monolayer (ML) molybdenum disulfide (MoS2) have shown promising potential as a candidate of next‐generation nanoelectronic devices. The first first‐principles quantum transport investigation of the ballistic performance upper limit of sub‐10 nm ML MoS2 FETs with Ti electrode is provided. An extraordinary small subthreshold swing is obtained by taking advantage of a dual gate (DG) configuration. The ballistic performance upper limits of the sub‐10 nm ML MoS2 DGFETs are comparable with the best existing sub‐10 nm advanced silicon FETs. The 10 nm ML MoS2 DGFET can satisfy 35% and 54% requirement of the on‐state current of high performance and low power FETs of the next decade in the International Technology Roadmap for Semiconductors 2013, respectively.

Large size monolayer Molybdenum disulphide (MoS2) was successfully grown by chemical vapor deposition method under an atmospheric pressure. The electrical transport properties of the fabricated back-gate monolayer MoS2 field effect transistors (FETs) were investigated under low temperatures; a peak field effect mobility of 59 cm2V−1s−1 was achieved. With the assist of Raman measurement under low temperature, this work identified the mobility limiting factor for the monolayer MoS2 FETs: homopolar phonon scattering under low temperature and electron-polar optical phonon scattering at room temperature.

Tin disulfide (SnS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ) is a layered metal dichalcogenide semiconductor [1]. Its crystal structure and many of its electrical, optical and catalytic properties are similar to those of molybdenum disulfide (MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ) [2] which has received significant attention due to the large electron mobilities of over 500 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs that have been measured in monolayer MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> field-effect transistors (FETs) [3]. A potential advantage of SnS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> over MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> is its larger bandgap (2.3 eV for bulk SnS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> [1], compared to 1.2 eV for bulk MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> [2]), which may translate into smaller leakage currents and larger on/off ratios in FETs, especially when the channel length is small and the applied drain-source voltage is large. Recently, Song et al. reported an electron mobility of 50 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for FETs based on mechanically exfoliated SnS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> monolayers [4]. These monolayer FETs showed a subthreshold swing of 10 V/decade and a promising on/off ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , but similar to many metal dichalcogenide FETs reported in the literature, this large on/off ratio was obtained only when the applied drain-source voltage was very small (0.01 V). In addition, the FETs had a negative threshold voltage. However, for many applications, such as active-matrix displays and low-power logic circuits, positive threshold voltages and large on/off ratios at large drain-source voltages are more desirable. Here we demonstrate FETs based on mechanically exfoliated SnS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> multilayers with a thickness of several hundred nanometers that have relatively small field-effect mobilities (0.04 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs), but provide a steep subthreshold swing (4 V/decade) and a large on/off ratio (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> ) even when the applied drain-source voltages are quite large (10 V).