Abstract

The steadily increasing number of compute nodes in high-performance computing (HPC) systems calls for more efficient interconnection networks and application mapping strategies. Traditionally, the user applications are mapped onto a regular network with nearby compute nodes to reduce the network distances. However, it is likely that the rigid mapping limitation on regular topologies may largely delay the dispatch time when the workload is heavy at a short period. In this work, we target the applications with unknown communication patterns over random interconnection networks, which have drawn increasing attention in the HPC world due to their low diameter and low average shortest path length (ASPL). We propose to use topology embedding metrics, i.e., diameter and ASPL, for application mapping to overcome the rigid limitation on regular topologies. We investigate the time-space tradeoff among several application mapping algorithms using a compound application workload. Evaluation results show that, when compared to the baseline random connected topology mapping, the proposed diameter/ASPL-based topology mapping algorithms reduce up to 48.0% makespan and up to 78.1% average turnaround time and improve up to 1.9X system utilization when the instantaneous workload is heavy over random interconnection networks.

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