Abstract
Problem statement: In this study, a systematic study based on Technology CAD (TCAD) was taken up for the design and Virtual Wafer Fabrication (VWF) of strain-engineered MOSFETs in Si CMOS technology. Approach: A simple manufacturable process recipe was developed to induce uniaxial stress in channel region to obtain enhanced performance in CMOS in 45 nm technology node. Results: Using Synopsys Sentaurus Process simulation tool, high dopant activation and low Transient Enhanced Diffusion (TED) during processing are fully captured. A physics-based mobility model had been developed and implemented in Synopsys Sentaurus Device tool. Sentaurus Device was used to simulate device DC and AC characteristics and also to extract Vth, Ion and Ioff. Conclusion: Optimum process conditions required to meet a set of device specifications had been achieved via the Design of Experiment (DoE) study. Process Compact Model (PCM) was used for performance and manufacturability optimization.
Highlights
As MOSFET device dimensions approach their physical limits (Maiti et al, 2007a), Technology CAD (TCAD) tools that can accurately simulate Integrated Circuit (IC) fabrication process technology and device characteristics are indispensable for advanced technology development and manufacturing
We report on a systematic TCADbased study towards design and optimization of strainengineered MOSFETs in 45 nm technology node using Sentaurus TCAD tools (Synopsys, 2008a; 2008b)
We have presented the results of the Process Compact Model (PCM) studies via the variation of technological parameters for the optimization of strain-engineered MOSFETs
Summary
As MOSFET device dimensions approach their physical limits (Maiti et al, 2007a), TCAD tools that can accurately simulate IC fabrication process technology and device characteristics are indispensable for advanced technology development and manufacturing. TCAD has the power to analyze accurately the impact of process parameter variations on device characteristics and may be used to address and control process variability as needed for modeling the semiconductor manufacturing process. Generally a systematic Design of Experiments (DoE) run is performed. DoE can be systematically set up, with control over process parameters and arbitrary choice of device performance characteristics. The models developed from DoE are known as Process Compact Models (PCMs). They are analogous to compact models for semiconductor devices and circuits. PCM may be used to capture the nonlinear behavior and multi-parameter interactions in manufacturing processes
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