Abstract

To meet new trigger and data acquisition (TDAQ) buffering requirements and withstand the high expected radiation doses at the High-Luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. The triangular calorimeter signals are amplified and shaped by analog electronics over a dynamic range of 16 bits, with low noise and excellent linearity. Developments of low-power preamplifiers and shapers in the 130 nm CMOS technology are ongoing to meet these requirements. In order to digitize the analog signals on two gains after shaping, a radiation-hard, low-power 40 MHz 14-bit Analog-to-Digital Converter (ADC) is developed using a pipeline + Successive Approximation Register (SAR) architecture in the 65 nm CMOS technology. Characterization of the prototypes of the front-end components show good promise to fulfill all the requirements. The signals will be sent at 40 MHz to the off detector electronics, where Field-Programmable Gate Arrays (FPGAs) connected through high-speed links will perform energy and time reconstruction through the application of corrections and digital filtering. Reduced data will be sent with low latency to the first level trigger, while the full data will be buffered until the reception of trigger accept signals. The data-processing, control and timing functions will be realized by dedicated boards connected through Advanced Telecommunications Computing Architecture (ATCA) crates.

Highlights

  • The upgrade needs a number of boards with new ASICs and high

  • This development is going smoothly and is expected to be finished and tested before the start of the HL-LHC operation

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Summary

Road map of the upgrade

The LAr electronics upgrade is divided in two phases [3, 4] and has a free-running scheme in which all calorimeter data are digitized on detector at a rate of 40 MHz (the bunch-crossing frequency) and sent off detector with low latency for further processing, see figure 1. The Phase-I upgrade (to be finished early 2021) aims to provide higher granularity LAr data for the LAr trigger. This extended LAr information will be used in Run 3 of the LHC operation starting at that time. The LAr Trigger Digitizer Board (LTDB) located on detector and the LAr Digital Processing System (LDPS) located off detector need to be developed and installed during the Phase-I upgrade. During the Phase-II upgrade all other electronics modules (see blocks marked with blue squares in figure 1) needed for HL-LHC will be developed and installed

Phase-II front-end electronics upgrade
Calibration board
Phase-II back-end electronics upgrade
Summary
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