Development of Histogram Equalization Hardware By High-level synthesis

Abstract

High-level synthesis is a technology that converts a software program into hardware. High-level synthesis can greatly reduce the load of hardware design and development. An FPGA is a device that can implement any digital hardware at any time. The combination of high-level synthesis and FPGA has been attracting attention in the field of embedded devices where the life cycle of products is short and the demand for power-saving and high-performance products is high. High-level synthesis cannot convert pure software that describes the algorithm intuitively into high-performance and low-power hardware. High-level synthesis requires an input program that considers the hardware configuration in order to generate good hardware. In this paper, we develop hardware for histogram equalization to improve image contrast using high-level synthesis. In the description of the program, in addition to general methods such as fixed-point conversion, the description method we have developed is applied. Experimental results show that the histogram equalization hardware can achieve 2.3 times performance improvement compared to software implementation.