Development of a computational lithography roadmap

Abstract

While lithography R&D community at large has already gotten the mind set for 32nm, all eyes are on 22nm node. Current consensus is to employ computational lithography to meet wafer CD uniformity (CDU) requirement. Resolution enhancement technologies (RET) and model OPC are the two fundamental components for computational lithography. Today's full-chip CDU specifications are already pushing physical limits at extreme lithography k₁ factor. While increasingly aggressive RET either by double exposure or double patterning are enabling imaging performance, for CDU control we need ever more accurate OPC at a greater computational efficiency. In this report, we discuss the desire for wanting more robust and accurate OPC models. One important trend is to have predictive OPC models allowing accurate OPC results to be obtained much faster, shortening the qualification process for exposure tools. We investigate several key parameters constitute to accuracy achievable in computational lithography. Such as the choice of image pixel size, numbers of terms needed for transmission cross coefficients (TCC), and "safe" ambit radius for assuring accurate CD prediction. Selections of image pixel size and "safe" ambit radius together determine % utilization for 2D fast Fourier transformation (FFT) for efficient full-chip OPC computation. For IC manufacturing beyond ArF, we made initial observations and estimations on EUV computational lithography. These discussions pave the way for developing a computational lithography roadmap extends to the end of Moore's Law. This computational lithography roadmap aims to be a complement for the current ITRS roadmap on what does it take to achieve CD correction accuracy.