Development of a Broadband DC ‐Bias Included CSWPL Model for RF Power Transistors With Harmonic Information

In this work, a harmonic included canonical piecewise linear (CPL) function based quadratic poly-harmonic distortion (QPHD) model is presented. The proposed model employs the framework of the standard QPHD model, making use of the CPL functions for interpolation of the amplitude of the dominant input signal. Compared with the standard QPHD model, the model described in this work is able to predict transistor behavior at different levels of input powers with one single set of model coefficients. The harmonic information has also been added in this model to make it more complete. The model is validated in terms of both DC and RF behavior through simulated data of a 10 W gallium nitride (GaN) high-electron-mobility transistor (HEMT) over a wide range of load conditions and power levels. In addition, the model is implemented in advanced design system (ADS) with frequency-defined device (FDD), and applied for a broadband power amplifier (PA) design. Chebyshev low-pass topology is used for both input and output matching network design. Finally, a broadband PA is implemented with an average power added efficiency of 66.23%, an average power of 41.09 dBm, and an average gain of 13.09 dB across the operating frequency range from 0.6 to 1.7 GHz. The simulation results of the harmonic included CPL-QPHD model are highly matched with the measurement results of the designed PA, demonstrating the feasibility of applying the proposed model for broadband PA design.

Low Power Transmitter design requires to optimize the energy efficiencies of key building blocks including Voltage Controlled Oscillator, Mixer, and Power Amplifier (PA). Traditional Power Amplifier design for low power application use various classes of amplifiers such as Class A, Class AB, Class E to avoid output filters that degrades the output efficiency. Class-E PA is a nonlinear switching type PA which can ideally achieve 100% efficiency. Generally the output of the Power Amplifier should match with antenna's 50Ω resistance; this high efficiency has spurred many research interests on the design and analysis of Class-E PAs. The aim of the paper is to design a microwave PA which works in the narrow band range of 2.35-2.45GHz. This paper presents a new Class-E PA with a π-matching output network which produces increased efficiency. The proposed circuit consists of power amplifier stage along with the Pre-driver stage. The Pre-driver stage is an indispensable stage when we refer to the rest of power amplifier. The N-Channel Field Effect Transistor (NFET) Inverter with a serial inductor reduces the power consumption of the switching capacitance of the PA stage is used as the pre driver stage. The PA stage realised by NFET. In order to increase the efficiency of PA a parallel inductor is introduced to the conventional Class-E PA structure. The Proposed structure needs a supply voltage of 0.5 V. The structure is simulated using the Advanced Design System (ADS) simulator. The output of the simulator produces graph of current with time and voltage with time. The efficiency of the PA is also plotted using ADS. It is possible to achieve increased efficiency when the width of the transistor is reduced. The inductor introduced at the output stage also has an impact on the efficiency of the PA. The proposed PA finds applications in Bio-Telemetry, short distance communications etc.

In this paper, a broadband power amplifier (PA) using 10 W GaN transistors is designed, with the operating frequency band between 2 GHz to 3 GHz. The initial design of the PA is firstly optimized with the optimizer embedded in advanced design system (ADS), after that, it was further optimized using the proposed Bayesian optimization (BO) algorithm. The detail design and optimization procedure are given, and the optimized results are analyzed. The PA obtained by the twice optimization can achieve an output power (Pout) greater than 41.1 dBm, a power added efficiency (PAE) higher than 62.5 %, and a gain greater than 11.1 dB in the operating band, which is a significant improvement compared with the performance of the initial designed PA.

Due to the rapid development of telecommunication devices, operating speeds are getting faster and more power is being consumed by those devices. Therefore, there is a big concern on how to prolong the battery life in order to fit consumers’ needs. Power amplifiers (PA) at the front end of wireless equipment have drawn a big concern from engineers because of their large power consumption in the system. There is a lot research conducted on PA solutions for improving power-added efficiency (PAE) of amplifiers. PAE is a figure of merit representing how efficient the PA converts DC power to RF power. With PAE increased, the device is able to output the same amount of power with less DC power consumed. Non-linear Class-F and Class-F-1 PAs have drawn the most attention among all different classes of PAs from engineers because of their capability of outputting high power and providing good PAE. Class-F boosts up PAE by controlling the harmonic content at the output. Advanced Design System (ADS) from Agilent is used for design and simulation based on the ADS model of Cree’s CGH40010 high electron mobility transistor (HEMT). A high efficiency power amplifier is fabricated on RT/duroid 5870 high frequency laminate board. In this design, the harmonics at the input are controlled as well as the harmonics at the output. An input wave-shaping network is designed to shape the waveforms at the gate. In this case, the PAE is boosted 30% higher than the PA with only the output wave-shaping network. By terminating harmonics with proper impedances at the output, a square voltage waveform and a half-sine current waveform are obtained at the transistor drain terminal. The overlapping area between the voltage and current waveforms can be reduced as well as the active device power consumption. The final design operating at 1GHz produced a PAE of 89% with 38.35dBm output power in simulation and PAE of 78% with 38.7dBm output power as the result of the IEEE PA design contest. The thesis has shown the effectiveness of the Class-F PA to boost up PAE by preventing the 2nd and 3rd harmonic power from delivering to the load and shaping the waveforms at the transistor terminals. It also shows the benefit of using radial stubs in wave-shaping networks over open-circuit stubs.

Land Mobile Radios (LMR) are used by various emergency organizations such as military, fire and ambulance services. The main function of LMR is to transmit voice over a selective range of radio frequency and they are mostly battery operated. Power amplifier (PA) circuit of LMR has drawn a major concern from engineers because they consume enormous power from battery. More research is conducted on PA to find solutions for improving Power Added Efficiency (PAE). PAE represents a figure of merit that economically shows how efficiently the PA converts RF power to DC power. With PAE parameter increased the device can be able to produce output the same amount of power with less DC power consumed. Class-E power amplifier desires the most attention among different classes of PA from engineers because of their ability of providing high PAE and more harmonic suppression. In this paper, Advance Design System (ADS) software is used for designing and simulation. Class-E PA is designed, harmonics are suppressed at the output. The final design operates at the frequency range of 136-174MHz with PAE of 92.39% by delivering 28.75dBm output power and the effectiveness of Class-E PA is boosted to suppress second order harmonics by 91.675dBc.

This article examines the effects of Bayesian optimization (BO) with different covariance functions on the optimization of a radio frequency power amplifier (RFPA). An initial PA is designed based on a Chebyshev low‐pass topology using a 10 W Gallium Nitride (GaN) transistor. The objective function is established in a novel manner. The performance of the initially designed PA was optimized by using various BO algorithms, including two different acquisition functions and five different covariance functions. Both simulation and measurement results indicate that the kernel squared exponential (KSE) and Matérn32 covariance functions provide the best option for optimizing PA by BO. A broadband power amplifier (PA) operating at a frequency range from 2.5 GHz to 3.5 GHz has been developed with an output power (Pout) greater than 40.8 dBm and a power‐added efficiency (PAE) greater than 65%.

Class F power amplifiers increasingly have widespread use cases in the modern portable mobile communications and higher efficiency operation due to base station. This paper focuses on the design of sub 6 GHz class-F Power Amplifiers (PA) to ensure maximum output power and gain using Gallium nitride– High Electron Mobility Transistor (GaN HEMT). The work also aims to analyze stability and Power Added Efficiency (PAE) using Advanced Design System (ADS) software. Simulations for DC characteristics of the GaN HEMT transistor are performed, stability circles are simulated, and stability factor values have been noted, using ADS software. Stability analysis involves measurements to examine the conditions that may lead to unstable behavior of the PA. The load pull analysis followed by impedance matching is done to transfer maximum power from amplifier stage to load. The input and output network has been designed using transmission lines and incorporated in the final circuit of the PA design. Using the LineCalc tool, the values of electrical parameters are used in the respective MLIN and TLIN circuits, and the respective matching networks are designed at the input side and output side. The amplifier stability factor is 2.276 and the maximum PAE is 65.75%. The maximum output is 39.83 dBm. The layout for the PA network using ADS software has been obtained.

In advanced wireless communication systems, a rapid increase in the mobile data traffic and broad information bandwidth requirement can lead to the use of complex spectrally efficient modulation schemes such as orthogonal frequency-division multiplexing (OFDM). Generally, complex non-constant envelope modulated signals have very high peak-to-average ratios (PAPR). Doherty Power Amplifier (DPA) is the most commonly used power amplifier (PA) architecture for meeting high efficiency requirement in advanced communication systems, in the presence of high PAPR signals. However, limited bandwidth of the conventional DPA is often identified as a bottleneck for widespread deployment in base-station application for multi-standard communication signals. The research in this thesis focuses on the development of new designs to overcome the bandwidth limitations of a conventional PA. In particular, the bandwidth limitation factors of a conventional DPA architecture are studied. Moreover, a novel design technique is proposed for DPA's bandwidth extension. In the first PA design, limited bandwidth and linearity problems are addressed simultaneously. For this purpose, a new Class-AB PA with extended bandwidth and improved linearity is presented for LTE 5 W pico-cell base-station over a frequency range of 1.9-2.5 GHz. A two-tone load/source-pull and bias point optimization techniques are used to extract the sweet spots for optimum efficiency and linearity from the 6 W Cree GaN HEMT device for the whole frequency band. The realized prototype presented saturated PAE higher than 60%, a power gain of 13 dB and an average output power of 36.5 dBm over the desired bandwidth. The proposed PA is also characterized by QAM-256 and LTE input communication signals for linearity characterization. Measured ACPRs are lower than -40 dBc for an input power of 17 dBm. The documented results indicate that the proposed Class-AB architecture is suitable for pico-cell base-station application. In the second PA design, an inherent bandwidth limitation of Class-F power amplifier forced by the improper load harmonics terminations at multiple harmonics is investigated and analyzed. It is demonstrated that the impedance tuning of the second and third harmonics at the drain terminal of a transistor is crucial to achieve a broadband performance. The effect of harmonics terminations on power amplifier's bandwidth up to fourth harmonics is investigated. The implemented broadband Class-F PA achieved maximum saturated drain efficiency 60-77%, and 10 W output power throughout (1.1-2.1 GHz) band. The simulated and measured results verify that the presented Class-F PA is suitable for a high-efficiency system application in wireless communications over a wide range of frequencies. In the third PA design, a single- and dual-input DPA for LTE application in the 3.5 GHz frequency band are presented and compared. The main goal of this study is to improve the performance of gallium-nitride (GaN) Doherty transmitters over a wide bandwidth in the 3.5 GHz frequency band. For this purpose, the linearity-efficiency trade-off for the two proposed architectures is discussed in detail. Simulated results demonstrate that the single- and dual-input DPA exhibited a peak drain efficiency (DE) of 72.4% and 77%, respectively. Both the circuits showed saturated output power more than 42.9 dBm throughout the designed band. Saturated efficiency, gain and bandwidth of dual-input DPA are higher than that of the single-input DPA. On the other side, dual-input DPA linearity is worse as compared to the single-input DPA. In the last PA design, a novel design methodology for ultra-wide band DPA is presented. The bandwidth limitation factors of the conventional Doherty amplifier are discussed on the ground of broadband matching with impedance variation. To extend the DPA bandwidth, three different methods are used such as post-matching, low impedance transformation ratio and the optimization of offset line for wide bandwidth in the proposed design. The proposed Doherty power amplifier was designed and realized based on two 10 W GaN HEMT devices from Cree Inc. The measured results exhibited 42-57% of efficiency at the 6-dB back-off and saturated output power ranges from 41.5 to 43.1 dBm in the frequency range of 1.15 to 2.35 GHz (68.5% fractional bandwidth). Moreover, less than -25 dBc ACPRs are measured at 42 dBm peak output power throughout the designed band. In a nutshell, all power amplifiers presented in this thesis are suitable for wideband operation and their performances are satisfying the required operational standard. Therefore, this thesis has a significant contribution in the domain of high efficiency and broadband power amplifiers.

Microwave power transmission (MPT) is one of the most promising techniques for long-distance wireless power transmission. Power amplifier (PA) is an essential part of MPT. However, the biggest problem existing in PA is the serious efficiency loss at low input power, meaning that it cannot work efficiently on a wide input power range. To solve the problem, this paper proposes a new impedance design method and establishes a simplified impedance mismatch evaluation model with only two parameters to precisely estimate the severity of impedance mismatch loss (SIML). This model can be readily utilized under any matching condition and accurately depict the impedance-efficiency characteristics with the impedance obtained by load pull. Based on the model, the impedance design strategy for maximum efficiency is derived. A 5.8GHz/20W high efficiency harmonic controlled PA operating on a wide input power range is constructed to verify the proposed model and impedance design strategy.

This paper presents the design and evaluation of a high efficiency power amplifier with high voltage capability. And power amplifier based on two-stage topology at frequency of 2.4 GHz ISM band. The optimization of source and load impedance for the proposed power amplifier is determined using smith chart or tuning system. Power output spectrum is designed including harmonic resonators up to 3rd harmonic. This power amplifier provides a excellent performance. In which we use the two-stage topology. The simulated power amplifier achieved maximum power added efficiency (PAE) of 34 %. The total Gain (S21) is 23.4 dB. And input return loss and output return loss is 13dB and 11 dB respectively. The proposed method is addressed to optimize power efficiency while maintaining good input and output matching. The design simulation process is using Advance Design System (ADS) software.

There are many methods for improving the efficiency of the power amplifier, one of which is Hybrid EER that we use. In this technique, the signal is divided into two parts. In a path the information in the envelope of the signal is detected and is applied to the drain of the transistor. By this method the voltage of the drain is variable and is related to the amplitude of the input signal. In another path the signal is fed to the RF amplifier. In this paper we introduce EER, ET and HEER techniques and explain the envelope amplifier. Design of the envelope amplifier is very important in the system; since it plays a chief role in the total efficiency. We have designed the power amplifier using the MRF6S27015N MOTOROLA transistor in LDMOS technology and applied HEER to our amplifier. It caused more than 50% of PAE in a wide range of input power.

The design of an ambient radio frequency (RF) energy harvesting system is introduced to replace the battery of the mass Internet-of-Things devices. This system can achieve high sensitivity with high efficiency over a wide input power range by optimizing the differential-drive cross-coupled (DDCC) rectifier and the load. The impedance of the dual-band four-port loop antenna array is directly conjugated to match with the rectifier, which reduces insertion loss of the matching network to improve efficiency. At 915 and 945 MHz for ISM and GSM bands, the rectenna can achieve high sensitivity of -30 dBm with 22% and 24% efficiency, high efficiency of 65% and 48% with -20-dBm input power, and a wide input power range from -30 to -18 dBm with 22-65% and 24-48% efficiency. The dual-band design explores the frequency diversity to harvest more RF energy from the environment, while the cross-shaped antenna array utilizes the space diversity to harvest RF energy from different directions with a compact size of 0.15λ x 0.15λ per antenna element (where λ is the free space wavelength at 915 MHz). This new harvesting system can provide output dc power of 21.4 and 2.95 μW in real-world outdoor and indoor ambient environments, respectively.

<span>The wireless communication networks in the smart grid’s advanced metering infrastructure (AMI) applications need 5G technology to support large data transmission efficiently. As the 5G wireless communication network’s overall bandwidth (BW) and efficiency depend on its power amplifier (PA), in this work, a two-stage class-J power amplifier’s design methodology that operates at 3.5 GHz centre frequency by utilizing the CGH40010F model gallium nitride (GaN) transistor is presented. The proposed design methodology involves proper designing of input, output, and interstage matching networks to achieve class-J operation with improved power gain over desired BW using the advanced design system (ADS) electronic design automation (EDA) tool and estimating its integration feasibility through active element-based design approach using the Mentor Graphics EDA tool. The proposed PA provides 54% drain efficiency (D.E), 53% power added efficiency (PAE) with a small signal gain of 27 dB at 3.5 GHz and 41 dBm power output with 21 dB of improved power gain across a BW of around 400 MHz using 28 V power supply into 50 Ω load. By replacing the two-stage PA's passive elements with active elements, its layout size is estimated to be (15.5×29.2) μm2 . The results of the proposed PA exhibit its integration feasibility and suitability for the smart grid’s 5G wireless networks.</span>

We present in this work a reconfigurable broadband highly-efficient medium-power power amplifier (PA) design in 22nm FD-SOI for potential millimeter-wave (mm-Wave) 5G (5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> Generation) applications. The broadband PA is targeted to cover the key part of the 5G FR2 band (i.e., 24.25 to 43.5 GHz), with P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> ~16 dBm and high power-added-efficiency (PAE) and excellent linearity. The post-layout parasitic extracted (R+C+CC) simulations performed in Calibre suggest this PA reaches max. PAE > 35% around 20 GHz, while still maintaining higher than 16% max. PAE across the entire 20 GHz - 50 GHz band. Using an LTE 64-QAM modulated 250 MHz input at 28 GHz, this design boasts an impressive simulated linearity performance with ACLR <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-</sup> /ACLR <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1+</sup> = -36.6/-36.2 dBc at P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> = 11.4 dBm. With the broadband, high PAE and linearity performance, this reconfigurable CMOS PA appears attractive for potential mmWave 5G applications.

The paper presents a compact power amplifier (PA) topology for reducing quiescent current and current consumption under power backoff operation. The final stage of the PA consists of two parallel transistor cells designed for two different output power operations. By switching between the two cells, terminated with different load impedances, through a unique bias control network, improved efficiency is achieved over a wide range of low output power compared to the conventional PA. A 1.95 GHz WCDMA InGaP/GaAs HBT PA module (PAM) has been developed to validate the proposed circuit. The PAM demonstrates a very low quiescent current of 20 mA. It exhibits 40.5% PAE (power added efficiency) and -40 dBc ACLR1 at 28 dBm Pout. At a backoff output power of 18 dBm, the PAM achieves 19% PAE with -41 dBc ACLR1. The current consumption under backoff operation has been reduced by over 40% compared to the conventional design.