Developing a Bus Functional Model for APB slave using Universal Verification Methodology

Abstract

Semiconductor chips are manufactured for different end applications. Memory controller chips are used in SSDs, while high-speed ethernet transceivers are used in datacenters. Be it for any end applications, all semiconductor chips consist of internal and external bus protocols. Internal bus protocols such as AMBA AHB, APB, and AXI are used to communicate data within the chip. External bus protocols such as SPI, I2C, and MDIO are used to transfer data in and out of chips using chip input-output ports. Verification of these bus protocols is crucial before taping out the chip else the chip might come out faulty and render useless. Verification of bus protocols can be done using less efficient traditional verification methods or by building a flexible verification environment using Universal Verification Methodology. In addition to that, Bus Functional Model can be developed to make the testbench more reusable. In this paper, the development of APB Bus Functional Model is discussed. The model is later used to do a functional verification of a simple Analog to Digital and Digital to Analog converter interfaced through APB protocol. Simulations are done using Synopsys VCS tool and GTK waveform viewer is used to analyze waveforms.