Abstract

AbstractModified block ciphers increase the performance and lower the time duration for high-speed applications. High-speed applications are mainly required for wearable medical devices, and compact devices which are implantable in the human body. Various security algorithm suffers due to inclusion of malicious and natural faults. The proposed model modifies the Midori block as light-weighted nature. This proposed algorithm introduces lower latency and less hardware complexity. The proposed model adds diagnosis algorithm in different stages of the work flow. Diagnosis algorithm reduces the fault value to the minimum. The fault diagnosis systems implemented with nonlinear S-box layer and beat structures. The beat structure includes 64-bit and 128-bit Midori symmetric key ciphers. The designed systems are benchmarked on a field programmable gate array (FPGA) with injected faults. The proposed light-weighted block cipher blocks yields, good energy efficiency rate and implemented using VHDL code.KeywordsFault correctionLower block cipherField programmable logic array gate (FPGA)Midori blocks

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.