Designs of K-Band Divide-by-2 and Divide-by-3 Injection-Locked Frequency Divider With Darlington Topology

Abstract

This paper presents divide-by-2 and divide-by-3 injection-locked frequency dividers (ILFDs) using a Darlington cell in a TSMC 0.18- $\mu$ m CMOS process. The Darlington cell has higher transconductance than the traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-2 ILFD to achieve lower power consumption and wide locking range. This work provides an analytic method to choose the injector size for widening the locking range and lowering the power consumption. The measured locking range of the proposed divide-by-2 ILFD is from 20.5 to 22.9 GHz. The measured operation range of the divide-by-3 ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are ${-}{\hbox{138.3}}$ and ${-}140.35$ dBc/Hz at an offset of 1 MHz when the input referred signals have phase noises of ${-}{\hbox{132.54}}$ and ${-}{\hbox{131.5}}$ dBc/Hz, respectively. Meanwhile, both phase noise differences with respect to injection signal are 5.76 and 8.85 dBc, which are close to the theoretical values of 6 and 9.5 dBc. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 $\,\times\,$ 0.75 mm $^{2}$ and 0.77 $\,\times\,$ 0.79 mm $^2$ , respectively.