Abstract
Hardware accelerators for signalprocessing applications, such as finite impulse response (FIR) filters, MPEG motion vectors, and autoregressive filters, are frequently used in consumer electronics (CE) devices. Hardware accelerators are typically used to improve performance, but there are tradeoffs in their use, such as silicon area and energy. High-level synthesis (HLS) of hardware accelerator design involves critical decision-making steps, such as the design space exploration (DSE) of resources, scheduling, allocation, and binding. Exploring an optimal hardware design solution comprising an array of resource types is a complex problem and requires intelligent decision making in an automated manner. The exploration process of an optimal design solution is considered a difficult problem, as it involves tradeoffs between conflicting parameters of hardware area and execution time among innumerable candidate design variants.
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