Design techniques for embedded EEPROM memories in portable ASIC and ASSP solutions

Abstract

Design techniques for embedded EEPROM memories working under a wide supply voltage range are described. First, a current controlled ring oscillator for stable programming pulse generation has been developed. For supply voltage values ranging from 2 /spl nu/ to 3.5 /spl nu/, in the [-40/spl deg/C-85/spl deg/C] industrial temperature range, less than 30% of oscillation period variation has been measured. Moreover, this oscillator can be completely turned off in stand-by mode for power saving concern. Techniques for read optimization under the constraints of portable systems are also addressed. First, the advantage of using two oxide thickness advanced process for logic delay optimization of EEPROM memories is evaluated, and the gain obtained using the ATMEL 56.8 K mixed memory, 0.35 /spl mu/m digital process is reported. Then, a word line boosting technique used to amplify the available memory cell current is described. Thanks to the boost, current sensing delay remains acceptable even for supply voltage values under 2 /spl nu/. In addition, address transition detection (ATD) based cut off circuitry is used to minimize the power consumption at higher values of the supply voltage. A 32 k/spl times/16, 1.8 /spl nu/-3.3 /spl nu/ embedded memory has been designed using the proposed techniques. 170 ns typical access time (290 ns in process and temperature worst case) has been simulated at 1.8 /spl nu/, with an average current consumption lower than 3 mA at 3.3 /spl nu/ when reading at 3.3 MHz frequency.