Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code

Abstract

In this paper, we present an all-analog implementation of the rate-1/3, block length 40, UMTS turbo decoder. The prototype was designed and fabricated in a 0.35 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$mu$</tex> m CMOS technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast BER simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-1/3 analog turbo decoder for UMTS defined in the 3GPP standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical.