Design of Reconfigurable PA Based on Spoof Surface Plasmon Polaritons

We present a broadband dual-channel power amplifier (PA) with crosstalk suppression for multi-input multi-output (MIMO) communications. Operation of MIMO system with crosstalk is theoretically evaluated for two popular coding schemes including the space-time coding and linear precoding. Design challenges of a multi-channel PA on a single chip are investigated and circuit techniques, including second-harmonic trapping integrated into the output matching network and the use of back-via lines to isolate the channels, are proposed to mitigate the inter-channel crosstalk. A fully integrated dual-channel PA prototype, implemented using a 250-nm GaN-on-SiC process, provides 34.9–36.3dBm output power, 44–49% power-added efficiency (PAE), 11.3–12.3 dB power gain, 31.0–34.2 dB second-harmonic rejection, and −28.1 dB to −25.7 dB inter-channel crosstalk across 4.5–6.5 GHz. For a 100-MHz 256-QAM signal with 7.2 dB peak-to-average power ratio (PAPR), the PA achieves 29.9dBm average output power, 30% average PAE, −38.2/−39.1 dBc adjacent channel leakage ratio (ACLR), and −28.2 dB (3.9%) rms error vector magnitude (EVM), without using digital predistortion (DPD). Effect of crosstalk on linearity of the dual-channel PA is also measured and it is shown that for a 256-QAM signal EVM can increase by 3–8 dB, depending on relative power levels of the two channels.

Activities have been carried out to determine the best electrical operating conditions of GaN HEMT that enable maximum power added efficiency at L-Band for Switch Mode Power Amplifiers (class F, inverse class F and class E). Satellite Radio navigation applications (Galileo) are targeted. Maximization of power added efficiency is of prime importance to save DC power consumption, reduce self heating effects and improve reliability of power amplifiers. At 50V drain bias, a maximum power added efficiency (PAE) of 72% and 40.3 dBm output power (Pout) are obtained using class-F operating conditions at 2dB gain compression while a 75% PAE and 41.0 dBm Pout are obtained using class E at 3dB gain compression.

Design and optimization of spoof surface plasmon polaritons based multi-octave power amplifier using PSO algorithm

This paper presents a compact transformer-based linear and efficient power amplifier (PA) in 0.13-μm SiGe:C BiCMOS for 5G applications. To reduce the form factor, an ultra-compact neutralized cascode PA core is proposed, which achieves a state-of-the-art power density. To obtain a gain flatness at 5G NR band n257 (26.50-29.50GHz), transformer-based input and output matching networks are designed. The PA demonstrates a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S_{21}$</tex> 3-dB bandwidth <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(BW_{-3\text{dB}})$</tex> of 10.5GHz from 23.5 to 34GHz. At 28GHz/29GHz, the saturated output power ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{sat}}$</tex> ) are 22.7/22.4dBm with power-added efficiency (PAE) of 38.1/39.8%. The PA also supports 64- and 256-QAM modulated signal tests without digital pre-distortion (DPD). Over 26-30GHz, for 4.8Gb/s 64-QAM signals with peak-to-average power ratio (PAPR) 8.3dB at −25dB EVM, this PA continuously achieves >16dBm average power ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{avg}}$</tex> ) with >11% PAE.

In this paper, a novel half mode substrate integrated waveguide (HMSIW) 10W power amplifier (PA) designed with HMSIW matching network (MN) is presented for the first time. The HMSIW-based matching network (MN) is designed with microstrip-to-HMSIW transition and an inductive metalized post in HMSIW. The impedance matching for the fundamental frequency 2.14 GHz is realized by moving the position of the inductive metalized post in the HMSIW. Both the input and output MNs are designed with the proposed HMSIW-based MN concept. One HMSIW-based 10W PA using GaN HEMT at 2.14 GHz is designed, fabricated, and measured. The proposed HMSIW-based PA can be easily connected with any microstrip or SIW-based circuit. Measured results show that the maximum power added efficiency (PAE) is 72.2 % with 40.7 dBm output power and the maximum gain is 20.1 dB. At the design frequency of 2.14 GHz, the size of the proposed HMSIW-based PA is comparable with other microstrip-based PAs.

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

This paper presents the design, the realization and the power characteristics of plastic low cost packaged symmetric Doherty Power Amplifiers (DPA) operating in the 5.5–6.5GHz bandwidth. A single input (SI-DPA) and a dual input (DI-DPA) DPAs are proposed based on two power bars composed of two GaN HEMT cells (8 fingers of 275μm unit gate width). Input and output matching networks are designed on passive GaAs MMIC technology. To our knowledge, it is the first published SI and DI-DPAs working in C band, designed using Quasi-MMIC technology and assembled in plastic package. The measured power results under Continuous Wave (CW) signal of the SI-DPA demonstrate a maximum output power (Pout) upper than 20W (43.5dBm) with 50% drain efficiency (dE), 42% power added efficiency (PAE), 11dB of insertion gain (GI) in the 5.5–6.5GHz bandwidth. At 6dB output power Back-off (oBo), the drain efficiency is greater than 35% (32% PAE). The DPA linearity has been investigated with a 256QAM modulation signal of 30MHz bandwidth and using Digital Pre-Distortion (DPD) leading to a 50dBc Adjacent Channel Leakage Ratio (ACLR) at a 34 dBm average output power. The designed DI-DPA is identical to the SI-DPA without input power splitter. It demonstrates that the adjustment of power ratio between the main and the peak amplifiers associated with adequate bias points, improves all the power performances: linearity, PAE, oBo and GI. The DI-DPA reaches a 12.5 dB GI, a maximum Pout equal to 44dBm (3.5dB gain compression) with 45% PAE. Moreover, in the same previous bandwidth, 40% PAE with 4° of AM/PM variation are obtained at 6dBoBo and 36% PAE (AM/PM=3°) at 8dBoBo.

This paper presents a fully integrated linear power amplifier (PA) in a 65-nm CMOS process for mm-wave 5G applications. The proposed linear PA employs a compact symmetrical 4-way parallel–parallel power combiner with a third-order intermodulation distortion (IMD3) cancellation method to achieve high linear output power with a high power-added efficiency (PAE). An on-chip 4-way parallel–parallel power combiner, which combines the output power from 8-unit PAs, is designed with a compact footprint ( $241\,\,\mu \text{m}\,\,\times 241\,\,\mu \text{m}$ ). Conventional series power-combining transformer based power combiners have poor symmetrical performance for the amplitude and phase of the input impedance among unit PAs owing to the parasitic effects of the power combiners. However, the proposed parallel–parallel power combiner, which is based on parallel power-combining transformer structures, shows good symmetrical performances among unit PAs. Moreover, an IMD3 cancellation method using a parallel–parallel power combiner is proposed in this work. The proposed IMD3 cancellation method can support high-order modulation signals without increasing the complexity and reduce the dependence for digital predistortion (DPD). Consequently, the proposed linearization method obtains a high linear POUT and PAE without DPD. The PA in 65-nm CMOS demonstrates a saturated output power (PSAT) of 23.2 dBm, a 15.9-dB power gain, a 1-dB compressed output power ( $\text{P}_{\mathrm {O,1dB}}$ ) of 22 dBm, and a peak power-added efficiency (PAE) of 33.5% at 28 GHz. The measured error vector magnitude with 100 Msym/s of 256/512-QAM is −31.2/−32.1 dB with average output power of 18.02/17.73 dBm, average PAE of 17.6/16.1%, and adjacent channel power ratio (ACPR) of −30/−33.1 dBc without DPD. To the best of the authors’ knowledge, the proposed PA demonstrates high output power with the highest PAE performance supporting 256/512-QAM compared to the recently published fully integrated mm-wave 5G CMOS PAs.

This letter presents a dual-mode multi-band second harmonic controlled SOI LDMOS power amplifier (PA). A mode selection switch is designed to have better power handing capability than a conventional switch, which improves performance in low power mode (LPM). To improve the PA's linearity in high power mode (HPM), second harmonic is controlled with the aid of a path for LPM. The PA, implemented with a 0.13- $\mu$ m SOI LDMOS process, operates in triple bands (band 5, 8, and 20) with dual power modes. It is measured using a 16 QAM long-term evolution (LTE) signal with a 10 MHz bandwidth. At 850 MHz, the results show 27.7 dBm average output power (Pout), 31.4 dB gain, and 31.4% power-added efficiency (PAE) with 4% error-vector magnitude (EVM) in HPM and 10.4 dB gain, 15.5 dBm Pout, and 22.5% PAE with 4% EVM in LPM with the LTE signal.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

This article presents the design techniques for a multimode multiband (MMMB) linear RF power amplifier (PA) with a high efficiency, suitable for wireless handset multichip modules. The PA operates with high efficiency at the saturated output power and maintains high linearity with an enhanced efficiency at the back-off power. It is, thus, able to operate in multimodes (saturated/linear) and covers multibands (814-915 MHz; bands: 5/8/18/19/20/26) without reconfiguration, representing a novel solution for the converged PA module architecture to reduce the number of PAs within the handset. A new technique to the handset industry, class-J, is adopted to improve the efficiency while maintaining the linearity. To the best of our knowledge, this work provides the first implementation of the class-J using the GaAs heterojunction bipolar transistor (HBT) technology in the multichip PA modules. The utilization of the GaAs HBT adds more degrees of freedom to enhance the linearity. A PA module, consisting of a GaAs HBT die mounted on a four-layer laminate, is designed. The die is fabricated using the flip-chip technology. The output matching network and the control/bias network are fabricated on the laminate using the printed inductors and the surface-mount device (SMD) capacitors. The results validate the design techniques, showing 2G power added efficiency (PAE) 62%, 2.5G error vector magnitude (EVM) ≤ 3%, and 3G adjacent channel leakage ratio (ACLR) of 5MHz ≤ -35 dBc. The design achieves a higher PAE than other reported reconfigurable and complex MMMB PAs, with comparable linearity.

A highly efficient sub-Watt X-band inverse class-F SiGe heterojunction bipolar transistor (HBT) cascode power amplifier (PA) is presented. With a multi-harmonic resonance filter and a low loss lumped-element Wilkinson power combiner as an output matching network, the inverse class-F operation is realized successfully and high output power and power added efficiency (PAE) are obtained simultaneously. A cascode configuration with a low base impedance termination and reduced voltage–current waveform overlap extends ${V} _{\rm{CE}}$ swing of the upper SiGe HBT in the cascode beyond BVCBO, leading to improvement in output power and PAE. As proof of concept, the proposed PA was implemented in a 0.13- ${{\mu }}\text{m}$ SiGe BiCMOS technology platform. Measured results shows 53.4% peak PAE with 26.1 dBm output power at 10 GHz, when operated on a 3.0-V supply. No performance degradation is observed after 24-h continuous mode operation. To the author’s best knowledge, this brief has the highest PAE among any Si-based X-band PAs with comparable output power, which demonstrates that the proposed harmonic-tuned Wilkinson power combiner approach is an appropriate solution for efficient PA design at X-band.

In this paper, we present a design approach for broadband harmonic-tuned monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Two harmonic matching networks are proposed for the realization of continuous class-B and class-F modes in an integrated PA. A design procedure is developed for integrated PAs using these matching networks to achieve high linearity, broadband operation, and compact chip area, in the presence of parasitic components and the physical limitations of the MMIC process. Two proof-of-concept fully integrated PAs are implemented in a 0.25-μm GaN-on-SiC process. Output power of 34.2-36.4 dBm with 40% to 49% power-added efficiency (PAE) is achieved in 4.2-7.0 GHz (51.6% fractional bandwidth), from the continuous class-B PA with only 1.5-mm 2 chip area. Furthermore, the continuous class-F PA achieves 36.2 dBm output power and 52% PAE at 5.0 GHz. The PAs are also characterized using QAM signals with wide bandwidth, in order to evaluate their performance for 5G wireless applications. For a 64-QAM signal with 100-MHz bandwidth and 8 dB peak-to-average power ratio (PAPR), the continuous class-B PA achieves 29.3 dBm average output power, 28% average PAE, and -25 dB (5.5%) error vector magnitude (EVM). The continuous class-F PA, tested using a 200 MHz 256 QAM signal with 8.5 dB PAPR, provides an average output power of 28.5 dBm, average PAE of 27%, and -28 dB (4%) EVM, without any pre-distortion.

A fully integrated monolithic power amplifier (PA) for DCS/PCS applications has been integrated in 0.25 /spl mu/m SiGe BiCMOS technology. The three-stages power amplifier delivers 31.8 dBm of output power (Pout) with 63% power added efficiency (PAE). A 100 /spl Omega/ differential input impedance power amplifier module (PAM) has been designed to validate the proposed circuit. The PA includes an on chip temperature compensated bias block. The bulky and expensive RF chokes normally used for the first and second stage have been integrated on-chip, in order to minimize the number of passive components into the module. The reported PA is planned to be used in an envelope elimination and restoration (EER) architecture with 3.3 V supply voltage. Furthermore, the PA can withstand up to 10:1 load voltage standing wave ratio (VSWR) at no permanent damage.

In this paper, a high-efficiency frequency-reconfigurable CMOS power amplifier (PA) design technique is presented at 24 and 28 GHz using integrated tunable neutralization and matching networks. To cope with the adverse effects of gate–drain capacitance ( $C_{\mathrm {gd}}$ ) in millimeter-wave (mm-wave) CMOS PAs in deep-submicrometer technologies, we propose a reconfigurable coupling-coefficient-based transformer. This technique provides optimum neutralization of $C_{\mathrm {gd}}$ in a common-source configuration, while enabling tunable neutralization in a frequency reconfigurable PA. Furthermore, to reconfigure the PA’s input and output matching networks, a low-loss frequency-reconfigurable matching topology using a switched substrate-shield inductor is proposed. The adopted matching network addresses the high loss in a conventional frequency reconfigurable matching approach, while facilitating high efficiency in the proposed PA design. Using the proposed techniques, a class-AB PA is fabricated in a 65-nm CMOS technology. This prototype achieves measured saturated power-added efficiency (PAEsat) of 42.6%, saturated output power ( $P_{o,\mathrm {sat}}$ ) of 14.7 dBm at 24 GHz, and 40.1% PAEsat, and 14.4 dBm $P_{o,\mathrm {sat}}$ at 28 GHz while occupying an active area of only 0.11 mm2. At 24 and 28 GHz, the PA is tested under 16 and 64-quadrature amplitude modulation (QAM) signals with 250 MHz of channel BW. The PA achieves modulated PAE of 15.2%/14.1%, error vector magnitude of −26.4/−26.6 dB, and adjacent channel leakage ratio of −30/−32 dBc at an average output power of 7.1/7 dBm for a 64-QAM signal with 250-MHz BW at 24 and 28 GHz, respectively. To the best of the author’s knowledge, the design presents one of the highest PAEs among mm-wave CMOS PAs reported to date, while it also supports multiband operation.