Design of high-speed low-power differential dynamic-like static CMOS circuit families

Abstract

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. The delay and power calculations of both feedback-switch logic (FSL) and cascode voltage switch logic (CVSL) in terms of adder and logical design has been observed. Feedback-switch logic (FSL) is a clockless differential circuit family that is suitable for high-speed and low power because it offers fast switching, reduced capacitance and input-switching dependent activity factor without the need of clock connection. Feedback-switch logic circuit provides the output and its complement from a single side of the gate. Cascode voltage switch logic (CVSL) is a differential circuit family since it uses both true and complementary input signals and computes both true and complementary outputs. The logic function and its complement are implemented using fast NMOS networks. Thus, clockless CVSL gates offer reduced input capacitance.