Abstract
In this paper FIFB, FIEB and FISB Carry Save Adders and Wallace Tree Adders are designed, encoded in Verilog and simulated using Cadence Software. The 180 nm CMOS technology is used for implementation of adders. The simulation results are compared for power consumption, delay, silicon area and dynamic power dissipation. As the length of inputs increase, power dissipated, silicon area and delay increase in both Carry Save Adder and Wallace Tree Adder. Compared to traditional CSA, the proposed Wallace Tree Adder is found to have shorter delay, lesser power dissipation and lesser silicon area and hence more cost efficient and a better option for real-time applications.
Highlights
The necessity and popularity of portable electronics is driving designers to endeavor for smaller area, higher speeds, longer battery life and more reliability
The Wallace Tree Adder is more cost effective and has a shorter delay across the critical path because the number of adders needed on the critical path is reduced compared to Carry Save Adder
Since the design uses less adders than conventional carry save adder design, it is faster, but takes up less area and cost less to manufacture. Another benefit of using less adders is that less transistors are needed, and less power is consumed by the device
Summary
The necessity and popularity of portable electronics is driving designers to endeavor for smaller area, higher speeds, longer battery life and more reliability. Power and delay are the premium resources a designer tries to save when designing a system. The most fundamental units in various circuits such as compressors, comparators and parity checkers are full adders. Other potential applications of these adders are ALU, digital signal processing, counters, graphic processors, calculate addresses and code compressor. Enhancing the performance of the full adders can significantly affect the overall system performance. The data path consumes roughly 30% of the total power of the system. Adders are an extensively used component in data path and careful design and analysis of adders is required
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