Design of Fault Tolerant Single RAM-Based Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Parseval Checks

Abstract

AbstractWith the increase in demand for various features in electronic devices, development of these devices with less area and low power has become a prominant research area. This can be achieved by technology scaling, which makes the design simple and efficient at the cost of vulnerable to some faults. Soft errors are one such faults whose occurrence may disturb the operation of the device for an event, which may degrade the device reliability. Therefore, in most of the systems, preferably, there is a need for protection of vital elements. In many systems, the operation of several similar modules is observed, to process parallel data at a time. The Fast Fourier Transform (FFT) processor is one such thing in various diversified fields such as Digital communications, Bio-medical applications, Signal processing systems, etc. The Real Fast Fourier Transform (RFFT) is a type of memory-based FFT architecture. It can be optimized by its memory usage and processing element optimization. The single RAM-based RFFT architecture is of that kind. In this paper, the fault tolerant single RAM-based parallel RFFTs is proposed using a protection scheme that rely on conventional Error correction codes (ECC) and Parseval checks. This proposed architecure is implemented on virtex-6 and 7 devices using Xilinx ISE 14.2v tool. The results show that the proposed architecture performs better in terms of area and delay as compared to the existing ones.KeywordsSoft ErrorsReal Fast Fourier Transform (RFFT) ArchitectureSingle RAM-based RFFTError Correction CodesParseval ChecksField Programmable Gate Arrays (FPGA)