Abstract
The CMOS technology has been pushed by the constant scaling down of the feature size to approach its theoretical and functional limitations. In order to achieve low power, area and delay parameters new distinct technologies are evolving to replace the CMOS technology. Quantum dot cellular automata (QCA) is one technology which is used to model different arithmetic circuits. In QCA technology, the design of the adder is a fundamental requirement for a high performance arithmetic device. The heart of the arithmetic device in the processor is the BCD adder. In this paper BCD adder for QCA is implemented with five input majority gates. The new approach has tested and the delay of the recently proposed existing systems and the new system has been analyzed by using Xilinx software. The delay of new design is minimized when contrast with the three input and combination of three and five input existing systems.
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