Design of an Iteration-Reduced LDPC-CC Decoder Based on Compact Decoding Architecture

Abstract

In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10–4 and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.