Abstract
This work presents the design of a high-frequency on-chip sinusoidal signal generator based on a calibrated harmonic cancellation strategy. The proposed generator employs a digital shift-register to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using a harmonic cancellation strategy in a simplified current-steering DAC with only five branches. The proposed architecture allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28 nm FDSOI design are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 70 dB of SFDR for a generated sinusoidal signal at 166 MHz.
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