Abstract
In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier (LVTSCR), a novel LVTSCR with embedded clamping diode (DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+ implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+ implant region and the n+ bridge, which helps to improve the holding voltage and decrease the snapback region. The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse (TLP) tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.
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