Design of a Low-Power Phase-Frequency Detector and Gain-Boosting Charge Pump for GHz-Range Applications in 180-nm CMOS Technology

Problem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it is meant to be a low cost communication system. Phase Locked Loop is responsible on carrier frequency selection in a communication system. It is the most power consumer block in the transceiver as well. The objective of this study was designing a low power fully integrated integer-N PLL frequency synthesizer targeting the 2.4 GHz band IEEE 802.15.4 Std zigbee. Approach: Minimizing total power consumption of PLL was achieved by introducing a novel design of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. The proposed PFD used only 12 transistors and it preserved the main characteristics of the conventional PFD with a simple architecture. The Charge Pump (CP) was single-ended source switch to save power and minimize mismatches. The Voltage Controlled Oscillator (VCO) spans from 4.737-4.977 GHz band using LC resonator. The VCO worked at double the frequency band to avoid local oscillator leakage and feed through. The integer N divider used a 15/16 dual modulus. Results: The proposed PLL was designed using Silterra 0.18 um CMOS process. It consumed 3.2 mW with 1.8 voltage supply. Phase noise is-113.4 dBc Hz-1 at 1 MHz. The proposed PFD works up to 2.5 GHz with free dead zone. The Charge Pump (CP) works with 20 uA, lock-in time is 27 us and total die area is 1×2 mm. All results were taken from extracted layout simulations. Conclusion: The results of this study indicated that a PLL can work with less power consumption and save the transceiver battery. The proposed PFD was suitable for high speed applications.

Quantum-dot cellular automata (QCA), which has very high speed and very low area and power consumption, is one of the proposed nanotechnologies to design digital electronic circuits. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are two important blocks in transceiver circuit design. The phase-frequency detector (PFD), which measures the phase and frequency differences of two signals, is one of the main blocks in PLLs and DLLs architectures. In this paper, two novel phase-frequency detector designs have been proposed in QCA technology using rising and falling edge D flip-flops with reset ability. The proposed PFDs can provide the basis for designing larger circuits such as phase-locked loops and delay-locked loops that are widely used in communication systems. The two proposed structures for the phase-sensitive detector in quantum cellular automata technology, which detect the phase differences of rising and falling edges of their inputs, are composed of 174 and 170 cells, occupying only 0.27 and 0.26 μm2, respectively. Smaller area, better jitter performance, smaller glitch and reset path time, higher operating frequency and lower power consumption are the main advantages of proposed designs in comparison with CMOS PFDs. All the simulations are done by QCADesigner software and QCAPro Software.

This paper presents the design of a novel Phase Frequency Detector (PFD) and Charge Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our proposed PFD technique can eliminate the effect of missing edge and phase ambiguity problems in conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and charge injection error problem with this new design technique. The design charge pump current mismatch has been checked in 0.13 µm CMOS process and worst case mismatch error is 0.025 µA for a control voltage range from 0.25 V to 1.0 V for a 1.2 volt supply voltage. Phase noise performance of the proposed PFD and CP circuit is about −117.3 dBc/Hz at 1 MHz offset frequency for a load capacitance of 10 fF. Current noise of our PFD and CP circuit has been measured from the transistors level simulation to find the phase noise of the fractional-N PLL, for output frequency of 2.2 GHz with 40 MHz reference signal in CppSim system simulator. Proposed PFD and CP switching circuit's phase noise performance shows the 17.36 dB improvement compare to the NOR based PFD and 7.4 dB improvement compare to the NAND based PFD topology. Also, the effect of CP current mismatch and dc offset current at any of the current source or sink has been incorporated to check the effect on spur and phase noise of the fractional-N frequency synthesizer. In addition, charge pump current noise and phase noise modelling has been done here to find the output phase noise of the PLL considering the PFD and CP output current noise measured in transistor level in 0.13 µm CMOS.

This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs two rail-to-rail OP amplifiers to minimize the mismatch between the charging and the discharging current, which minimizes the steady-state phase error in a PLL and reduces the reference spurs. Moreover, a simple but effective technique is proposed to suppress the glitches of the output current, which also decreases the level of reference spurs in a PLL and at the same time increases the dynamic range of the CP. A PLL adopting the proposed PFD and CP is fabricated in TSMC 0.13um 1.2V CMOS process, and test results indicate that the PLL can achieve −56dBc reference spur level.

The main purpose of this thesis is to design a part of integrated circuits for a non-invasive wireless intraocular pressure (IOP) monitoring system. In our plan, the IOP system has three main parts: the sensor unit, the reader unit, and the calculation unit. The sensor unit includes a rectifier, a low dropout linear regulator (LDO) and a voltage-controlled oscillator (VCO). The reader unit comprises a receiver and a transmitter. The receiver is composed of a low noise amplifier (LNA), a mixer, a 2.2GHz phase-locked loop (PLL), and a frequency-to-voltage converter. The transmitter consists of a 5.8GHz PLL and an pre-amplifier for driving an off-chip PA. This thesis targets on the designs of a 2.4GHz voltage-controlled oscillator (VCO) at the sensor unit and a 5.8GHz PLL at the transmitter unit, a 2.2GHz PLL and frequency-to-voltage converter at the receiver unit. The last two circuits are for the reader unit. The circuits mentioned above are all fully-integrated in a CMOS process, respectively. The goal of our integration is to convert the intraocular pressure into a voltages value that can be processed by the calculation unit. In this thesis, all of the chips are fabricated in TSMC 0.18-μm 1P6M CMOS technology. In the 5.8GHz PLL and the 2.2GHz PLL circuits design, we add a “clear” signal to avoid the PLL performance influencing from the uncertainty of trigger signals. We also use a longer delay-cell chain to solve the “dead zone” problem in the phase-frequency detector (PFD) design. The charge pump circuit design is implemented by a rail-to-rail error amplifier to overcome the process variation and the current mismatch problem, so that the jitter and phase noise performance of VCO are improved simultaneously. For the loop filter design, we use an off-chip loop filter and an on-chip loop filter, respectively, with the capacitive multiplication technique in our two different PLL designs. The voltage-controlled oscillator designs are implemented by PMOS-only LC VCO and CMOS complementary LC VCO, respectively, too. In these two different designs, one of the reference signals is 100MHz and the other is 50MHz, in order to achieve the integration of 2.4GHz receiver and 5.8GHz transmitter circuits into a single chip for the reader unit. For the divider designs, the use of CML or MMFD topology is determined by which reference frequency we used. All PLLs mentioned above are working under a 1.8V power supply, expect for the CMLs and buffers with power-supply lies of 1.5V for reducing power consumption. The chips occupy an area of 1.82 mm2 (1.455mm × 1.25mm) and 3.1 mm2 (2.05mm × 1.51mm), respecitvely, in our two designs. The output power levels of VCOs are -5.731dBm and -11.89dBm, respectively, for the two different designs. The total power consumptions are 39.58mW and 36.85mW. The measured phase noise is -105dBc/Hz at 1MHz offset with a reference spur of -43dbm for the 2.2GHz PLL. In the frequency-to-voltage converter design, the RF signal down-converted by the mixer to the IF signal will be used as input reference frequency. The phase frequency detector and the charge pump are implemented by the ways similar to those PLLs mentioned above. While, the VCO is a current-starved ring oscillator. In our application, this converter mainly read out the variation of control voltage of the VCO, so the ring oscillator is not based on the differential delay cell topology which has better phase noise performance. In the loop filter design, a unit-gain buffer is used to readout the voltage variation at the output of loop filter with less loading effect. The circuit operates at a 1.8V power-supply and it consumes an area of 2.91mm2 (1.48mm × 1.97mm). In the sensor circuit design, the proposed VCO is implemented with a CMOS complementary LC VCO architecture. The wireless power transmission technique is adopted for power supply. To fit for the SAR standard, we set our specification of supply voltage at 1.5V with DC current 1.2mA to achieve the low-power design. And we also use a L-type matching network to do the co-simulation with antenna. The chip area is 1.53mm2(1.29mm × 1.183mm).

Delay Locked Loops (DLL) adapted in various applications due to its low power characteristics. Aggressive power demand in sensors, medical devices and new communications applications with embedded DLL has affected by Phase Frequency Detector (PFD) design techniques. This paper presents a review of various PFD in DLL design based on their main parameters including dynamic logic PFD topologies, PFD important parameters and issues total power consumption as well as their design trade-offs. This review paper gives a guideline to the future researchers for designing high speed and low power PFD.

This paper presents the performance analysis between two different Phase Frequency Detector approaches with Charge Pump. The Phase Frequency Detector (PFD) is an important building block of phase locked loop (PLL). The conventional and modified architecture of phase frequency detector with charge pump are compared in terms of area and power consumption. The phase frequency detector and charge pump are designed and simulated using Cadence tool in GPDK 180nm technology. The modified phase frequency detector has either UP or DOWN signals at a time. The conventional PFD also has one output either UP or DOWN at a time. The charge pump varies VCONTROL voltage according to the UP or DOWN signal which in turn controls frequency of voltage controlled oscillator (VCO).

The frequency synthesizer is an important role of the transceivers in the wireless communication systems. Today, various kinds of standard specifications are proposed for the communication systems. A different specification would lead to different frequency synthesizer's design. This thesis takes into account the frequency synthesizer design for the multi-band orthogonal-frequency-division-multiplexing (MB-OFDM) ultra-wideband (UWB) system, especially for the needs of Group-1 and the Group-3 sub-bands, in which there are six frequency outputs. The different designs of frequency synthesizers will lead to different circuit area and power consumption. Therefore, how to reduce the complexity of the electric circuit integration while achieving the same function is the design key point. In this thesis, the frequency synthesizer was fabricated in TSMC’s 0.18m 1P6M CMOS process. Our proposed frequency synthesizer is composed of one phase-locked loop (PLL), two multiplexers, two dividers, and two single-sideband (SSB) mixers. The PLL is operated at 6336 MHz with a 264 MHz reference input. The PLL has to provides quadrature outputs for driving the SSB mixers, so a quadrature voltage-controlled oscillator (QVCO) is necessary. There are two types of output loads for the SSB mixers; one is a resistive type for the operation frequency 2640 MHz; another is an LC-resonant type for those operation frequencies are 7656, 7128, 6600, 4488, 3960, and 3432 MHz. The PLL in the proposed UWB frequency synthesizer uses a second-order low pass filter (LPF). In the past, PLLs may utilize off-chip LPFs for the design flexibility consideration. This way can help to reduce the chip fail problem, but it will possibly cause more noises in the PLL. In this thesis, we use the on-chip LPF design that can have lower noise and less pump current level. Therefore, the power consumption of the charge pump circuit can be reduced. To consider the area consumption of the whole frequency synthesizer, the use with capacitive multiplication technique on the LPF can make the capacitor area small and the jitter performance of the QVCO improved. The capacitive multiplication technique is implemented with the help of an OP amplifier. The primary contribution of this thesis is the integration of a PLL, which consists of a phase frequency detector, a charge pump, an on-chip low pass filter, a QVCO and four dividers. The charge pump is implemented by a rail-to-rail error amplifier to overcome the process variation and the current matching problem. The low pass filter use capacitive multiplication technique with a smaller capacitance value and thus the chip area can be reduced. Considering the cooperative use of the SSB mixers in our proposed frequency synthesizer, a novel quadrature TSPC divide-by-3 circuit has been proposed. The total chip area is 1.3 mm × 1.3 mm. The output power is -7.63 dBm. The measured average phase noises of the PLL is -86.07 dBc/Hz at 100kHz offset from the center frequency. That of -102.23 dBc/Hz and -127.31 dBc/Hz at 1 MHz and 10 MHz offset frequencies, respectively, from the center frequency can be obtained. The power consumption is 32mW and the reference spur is -49.4 dBm. The post-layout simulation has been done for our proposed frequency synthesizer. The two SSB mixers respectively with an RC load and an LC load totally consumes the power consumption of 17.04 mW. The two multiplexers respectively with the bi-ways and tri-ways in power consumption are 6.92 mW. The total power consumption is 65.08mW and the vdd is 1.5V. The layout area is 1.2 mm × 1.15 mm without PAD.

In this paper, a Phase Frequency Detector (PFD) Charge Pump (CP) and programmable frequency divider Phase Locked Loop (PLL) for Bluetooth Low Energy (BLE) are presented. It is implemented using 180nm CMOS technology. The programmable frequency divider consists of Dual Modulus Prescaler divide by 15/16, 7-Bit Programmable Counter (P), and 6-Bit Swallow Counter (S). The divider will operate between 2.4–2.48 GHz frequency with 40 channels frequency hopping. The design has been simulated with 1.8 Vdd and consumed 3.51mW power.

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the phase-frequency detector. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new phase-frequency detectors sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0.13 μm2 of an area and 1.5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

Performance and comparison of several architecture topologies involve low phase noise and high-speed phase frequency detector. Phase frequency detector is essential in Phase-Locked Loop. Phase frequency detector has many advantages over Phase detector (PD) and Frequency detector (FD) by detecting frequency and phase simultaneously. Charge pump based phase frequency detector is an important block for signal generation in the PLL. At higher frequencies, the challenges like phase noise, jitter, power consumption, and area arise. This article discusses these design challenges of phase frequency detector at higher frequencies. Parameters of different design topologies have been compared. This comparative study will help the researchers to choose the best design out of the given topologies.KeywordsPhase frequency detectorCharge pumpPhase-locked loop

This paper presents a very simple approach to design effective PFD (Phase Frequency Detector) and charge pump (CP) circuits for high frequency Phase-Locked Loop (PLL) applications. The PFD design uses only six transistors for the detection process, which reduces the chip area and power consumption of the PLL block. It also minimizes the dead zone and eliminates the reset path to reduce the delay. The output is passed through a buffer to suppress the distortion and to reduce the overall output noise. Phase noise has been reduced to -156 (dBc/Hz) at 1 MHz offset frequency. A simple current mirror based charge pump circuit is presented next. The charge pump design incorporates the use of transmission gates and transistors as capacitors to reduce switching error and clock feed through. The proposed design has a symmetric structure in terms of W/L ratios, transistor positioning and number of transistors in both up and down network which produces a stable charging operation and reduces the spurious jumps in the output voltage. The overall output noise including thermal and flicker noise of the complete design at high frequencies is as low as -213 db at 4GHz. The proposed design provides a high output voltage swing of 1.4V while operating at 1.5V supply voltage. The design has been implemented in 1P-9M UMC 90nm CMOS technology. Simulations show the effectiveness of the design in terms of lower power consumption, lower noise and reduced distortion.

As the key blocks of PLL (phase locked loop) circuits, PFD (Phase Frequency Detector) is dominated to the precision and stability of system, whereas CP (Charge Pump) offers a wide scale of frequency capture scale and fast locked performance. The structure of PFD using transfer gate dynamic D flip-flops and the structure with a wide input scale error amplifier for CP had been presented to achieve a high performance. In the end, the chip was taped out in the process of TSMC 0.18μm CMOS. The post-simulation results show that the PFD has correct logic function, whereas the charge pump current is stable at 100μA in the output range of 0.2V~0.8V, and the current mismatch is less than 0.4μA at output voltage range of 0.2V~0.8V, with total power consumption of 3mW with the power supply of 1V.