Abstract
The ATLAS Fast TracKer is a custom electronics system that will operate at the full Level-1 accept trigger rate, 100 kHz, to provide high quality tracks as input to the high level trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories and FPGAs. We present the advantages for the physics goals of the ATLAS experiment at LHC as well as the recent results on the design, technological advancements and test of some of the core components used in the processor.
Highlights
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The final system will have about 8000 AM chips and 2000 FPGAs, from different vendors and of different models. This huge computing power will be distributed on 32 data formatter (DF) boards, 128 associative memory boards-serial link processors (AMBSLP or AMB) and auxiliary cards (AUX), 32 second stage boards (SSB), and 2 FTK to Level-2 interface cards (FLIC)
Summarizing the amount of data passing through the DF, each board receives up to 32 Gbps from the ID read-out drivers (RODs), about 30 Gbps of data are sent to the core processors, while 40 Gbps of data can be sent to other DFs in the same shelf and about 25 Gbps to the DF in other shelves
Summary
All the functionalities mentioned in the previous section are implemented in specific electronic boards and cards, designed using VME and ATCA standards. The final system will have about 8000 AM chips and 2000 FPGAs, from different vendors and of different models. This huge computing power will be distributed on 32 data formatter (DF) boards, 128 associative memory boards-serial link processors (AMBSLP or AMB) and auxiliary cards (AUX), 32 second stage boards (SSB), and 2 FTK to Level-2 interface cards (FLIC). A description of each board type is presented in the following sub-sections
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