Design of a FPGA hardware architecture to detect real-time moving objects using the background subtraction algorithm

Abstract

Until now intelligent video analysis comprises a set of hardware, software and theoretical foundation, all intertwined for targets identification, location, tracking and even behavior forecasting from a scene with almost no human intervention, so as to facilitate people's daily management and resolve exceptional situations in good time. The moving objects detection is a fundamental process in an intelligent video system. And the real-time system tends to be a constraint in video processing applications. In view of the above-mentioned facts, this paper's proposal is the study of background subtraction algorithm and Field Programmable Gate Arrays (FPGA) to develop an architecture focusing on real-time moving objects detection in high-speed video using the background subtraction algorithm. First we discuss the basics of moving objects detection, background subtraction and FPGA, covering their main characteristics. In the second stage, we discuss the implementation of moving objects detection by the combination of background subtraction method and OTSU algorithm with the use of floating-point rounding method and pipeline structure based on FPGA features. Then a system is built involving video capture, display and moving targets detection using Lattice's ECP3 series FPGA to verify the detection performance. Then the implementation process is described in detail, and the end shows the performance on the proposed method and its practical utility for intelligent video analysis.