Design of a CMOS Tapered Cascaded Multistage Distributed Amplifier

Abstract

This paper presents the design and measurement of a distributed amplifier (DA) in a standard 90-nm CMOS process. To improve the gain and bandwidth (BW) of the DA, the use of an elevated coplanar waveguide line and also impedance tapering in the synthesized sections are proposed. The effects of elevation and shielding filaments on the impedance, loss, and effective dielectric constant of the transmission line are investigated and accompanied by measurements. A methodology for CMOS DA design is described that can take advantage of the multiple degrees of freedom in terms of device size, topology, and aspect ratio available in these processes. The fabricated tapered cascaded multistage DA achieves a 3-dB BW of 73.5 GHz with a passband gain of 14 dB. This results in a gain-BW product of 370 GHz. The realized 0-dB BW is 83.5 GHz and the input and output matchings stay better than -9 dB up to 77 and 94 GHz, respectively. The chip consumes an area of 1.5 mm times 1.15 mm, while drawing 70 mA from a 1.2-V supply.