Design of a CMOS Power Amplifier With Improved Linearity Through Second-Harmonic Filtering Based on Parasitic Capacitance Analysis

PurposeThe purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless communication systems with a higher data rate of transmission capacity and lower power consumption has increased tremendously. The radio frequency power amplifier (PA) design is getting more challenging and crucial. A PA for a 2.45 GHz IoT application using 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented in this paper.Design/methodology/approachThe design consists of two stages, the driver and output stage, where both use a single-stage common source transistor configuration. In view of performance, the PA can deliver more than 20 dB gain from 2.4 GHz to 2.5 GHz.FindingsThe maximum output power achieved by PA is 13.28 dBm. As the PA design is targeted for Bluetooth low energy (BLE) transmitter use, a minimum of 10 dBm output power should be achieved by PA to transmit the signal in BLE standard. The PA exhibits a constant output third-order interception point of 18 dBm before PA becomes saturated after 10 dBm output power. The PA shows a peak power added efficiency of 17.82% at the 13.24 dBm output power.Originality/valueThe PA design exhibits good linearity up to 10 dBm out the PA design exhibits good linearity up to 10 dBm output power without sacrificing efficiency. At the operating frequency of 2.45 GHz, the PA exhibits a stability k-factor, the value of more than 1; thus, the PA design is considered unconditional stable. Besides, the PA shows the s-parameters performance of –7.91 dB for S11, –11.07 dB for S22 and 21.5 dB for S21.

WLAN is a widely used standard telecommunication protocol. Currently IEEE802.11ac standard has some limitations along with the increasing need for fast communication and able to serve many devices. The development of the IEEE 802.11ax standard is expected to overcome these limitations. Some challenges on the design of power amplifiers also appear as the development of 802.11ax standard. Power amplifiers on the access point are expected to provide a minimum output of 30dBm. This paper explains the design and modeling of power amplifiers on access point using load pull method. Based on the design and test result using CGH27030 transistor with simulation approach harmonic balance obtained that the output power of half wave obtained optimum value 33,023 dBm at input value 19 dBm and EVM equal to 4,8%.

Novel linearity enhancement using body bias tuning for 24–28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24–28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at P out,1dB can be reduced to only out,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ∼ −24.5/−28.5 dBc at P out = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.

Developments within modern nonlinear measurement systems offer an increasing degree of flexibility to the microwave power amplifier (PA) designer. The PA designer has historically been a driving factor in setting the development directions of new measurement systems, fueling the paradigm, that PA innovations largely push new measurement requirements. It would appear that measurement system manufacturers are now the ones pushing the technology envelope. This paper discusses current trends within modern nonlinear measurement systems to determine who is leading whom and whether the aforementioned paradigm is shifting.

This thesis concentrates on the development of advanced large-signal measurement and characterization tools to support technology development, model extraction and validation, and power amplifier (PA) designs that address the newly introduced third and fourth generation (3G and 4G) wideband communication standards. By exploiting an innovative mixed-signal approach, the measurement systems developed within this thesis work extend the limits of the current state-of-the-art large-signal characterization in terms of bandwidth, power range, speed and functionality. As described in Chapter 1 these activities are needed to address the demands that follow from the evergrowing data transfer rates in modern telecommunication systems. Here the introduction of the new 3G and 4G communication standards, which make use of higher bandwidths and peak-to-average ratios, in combination with the necessity to reduce the power consumption of mobile networks, put very stringent demands on the power amplifier in the wireless transmitter. Since the PA is one of the dominant sources of energy consumption in the wireless network, it needs to be very efficient and linear over a wide frequency range and over a wide power span. Therefore, to accomplish this difficult mission, the PA designer has to rely on either an accurate nonlinear model of the active device to perform the design in a circuit simulator, or on device data resulting from load-pull measurements, which can accurately characterize the transistor performance parameters as a function of the load and source impedances at all frequencies of interest. In order to support the development of compact device models which include self-heating and trapping effects, isothermal measurement systems are required. Chapter 2 introduces the theory and the requirements for pulsed-RF and pulsed-DC measurements. Moreover, a new isothermal measurement system is presented, which provides the ability to measure with DC and RF pulses as short as 200 ns, while featuring a very high dynamic range (? 85 dB) under pulsed-RF conditions, which is independent on the duty-cycle. The system performance is discussed in detail through a set of benchmarks, and some examples on isothermal active device characterization are provided. The second and dominant part of this thesis introduces a revolutionary active harmonic load-pull approach. Load-pull device characterization is fundamental to all activities related to PA design and PA development, from technology development, to model extraction and validation, to the actual power amplifier design. For this reason Chapter 3 reviews conventional passive and active source and load-pull architectures, and discusses their basic limitations, with particular attention to the problems arising when characterizing devices with wideband complex modulated signals. Moreover, the requirements of active load-pull systems to perform high power measurements with complex modulated signals are also explained. To solve the problems of conventional load-pull systems when dealing with wideband modulated signals, a novel active harmonic load-pull system based on a mixed-signal approach is described in detail in Chapter 4. The system developed during this thesis work enables the measurement of active devices up to 120 MHz of modulation bandwidth, and allows arbitrary control of the refection coefficient in this band. Measurement data highlighting the system performance, and measurement results on active devices are presented. To enhance the process of developing new transistor technologies and their application in very efficient and linear PAs, in Chapter 5, a new approach for enabling high-speed multidimensional source and load-pull parameter sweeps is introduced. The method described allows any combination of multiple parameters (e.g., input power and/or fundamental and harmonic load impedance) to be swept, at a very high speed, while maintaining all other parameters (e.g., second harmonic source impedance) accurately controlled to a user-defined value. Moreover, several measurements are reported, with particular emphasis on the high-power capabilities of the system, both in CW as well as under modulated signal excitations. The option to measure time-domain voltage and current waveforms can provide significant insight into the actual device behavior, which benefits to power amplifier design, ruggedness evaluation, as well as to (database) model extraction and validation. In Chapter 6 the basic theory behind the measurement of high frequency time-domain voltage and current waveforms at the device reference planes are discussed, and an extension to the mixed-signal load-pull system described in the previous chapters is presented, with particular attention on the requirements of the calibration device used for the system calibration. Furthermore an approach for time-domain waveform analysis of multi-tone signals which are closely spaced in frequency is introduced. To highlight the most unique capabilities of the mixed-signal load-pull system developed in this thesis, Chapter 7 reports several relevant examples of significant applications. In particular an out-of-band linearity optimization of an HBT device, the characterization of a GaN device for high efficiency PA design, and some very high-power device measurements for base-station applications are described. Chapter 8 finishes the thesis and gives the most important conclusions and the recommendations for future work.

The CMOS RF transmitter was implemented to meet the requirement of IEEE 802.11a Wireless LAN Systems are presented in this thesis. The circuit design in this thesis is divided into two main parts including mixer and power amplifier, and that all implemented with the process of TSMC 0.18um 1P6M CMOS to show the higher performance in deep sub-micro process and overcome the difficulties we met. The first main part is on the design of up conversion mixer. We based on the Gilbert Cell structure and used base-band input signal of fully differential quarter to direct up conversion. Since this architecture modulates signal without an IF section circuit, the low frequency (Base-band) signal is direct up conversion to high frequency (RF). So this architecture can omit the design of IF circuit. Even though, since the frequency of transmitter is close to local oscillator, The leakage problem and injection pulling phenomenon becomes the drawbacks of this architecture that we must solve and overcome. Compared with the conventional architectures of mixer, we presented the circuit technique of current reuse, combined with Gilbert cell and architecture of differential balance. After all, this improved mixer has better performance in conversion power gain, noise figure, isolation and linearity for applied in IEEE 802.11a WLAN standard. The second main part is on the design of power amplifier. We adopt the two stage cascade with capacitance compensation schemes to improve the power gain and linearity of CMOS power amplifier for WLAN applications of IEEE 802.11a. The output power in this circuit design is over 20dBm(100mW) and fabricated in a standard 0.18um single-poly-six-metal (1P6M) RF CMOS process of TSMC. Compared with the conventional CMOS PAs used the thick oxide devices, The improved circuit can have the higher performance since the minimum channel length of thick oxide devices is 0.35um. But there are two main issues in the design of power amplifier in submicron CMOS process, namely, oxide breakdown and hot carrier effect. On the other hand, are reliability and lifetime issues of the circuit products. So, in this thesis, the self-biased technique is presented that relaxes the restriction due to hot carrier degradation in power amplifier and alleviates the need to used thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. Since the linearity requirement of the modulation signal in OFDM and 64-QAM for IEEE 802.11a is higher than the others, adopt the NMOS diode linearizer to improve the linearity in this design. Compared with the other linaer technique, for example, PMOS linearizer. There is no DC current consume in the improved method, and save much chip area compared with the conventional method of inductor biased. In addition, included the parallel inductor compensation technique to absorb the parasitical capacitance effect, makes the power amplifier have the higher performance in power gain. Our laboratory centred on the research of front-end circuit design. For the concept of SOC, we adopt the process of CMOS that can integrate with digital circuit. In the future, this transmitter will can complete in a signal chip of 802.11a transceiver with receiver and frequency synthesizer.

Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore power amplifiers are the most important parts of electronic circuits. This is why the designing of power amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also utilized for getting the good matching condition. The advanced design system (ADS) software is used for design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent power gain; is changed between 28.5 and 20dB with an output power of 12.45dBm at 1dB compression point. For the input reflection coefficient (S11) is varied between -20 and -42dB. While the output reflection coefficient (S22) is varied between -10 and - 49dB over the wide frequency band of 3.2-3.8GHz.

This paper presents a step by step design of power amplifiers at 2.4 GHz (for WLAN applications) and on-chip linearization of these amplifiers. CMOS power amplifiers are designed at 2.4 GHz with output power ranging from 30 mW to 100 mW with efficiency varying from 20%-40%. Two or three stages are cascaded according to the gain and efficiency requirements. The topology used for 2.4 GHz amplifier is also verified as a part of an FM transmitter at 900 MHz. All these integrated power amplifiers are not intended to have a very good linearity. At the later part of this work, feedforward technique is used for linearization of a 2.4 GHz two-stage power amplifier in 0.25 /spl mu/m CMOS8 process. The power output of the linear amplifier (in push-pull configuration) is 17 dBm with 20% efficiency. The in-band non-linearity (from two-tone simulations) is given by 3/sup rd/ order inter-modulation product and is about 40 dBc. For on-chip combining, transformers and baluns are used. All the circuits are simulated using CADENCE tools (ICFB). Inductors, transformers and baluns are designed and simulated using ASITIC tools. The power amplifiers are currently under fabrication in CMOS8 (0.25 /spl mu/m) and CMOS9 (0.18 /spl mu/m) processes.

This paper presents an experimental high-efficiency class-F power amplifier (PA) design, which integrates Rhodes's efficient low-pass matching network topology with the charge conservative, robust, and accurate WREN/COBRA nonlinear pseudomorphic high electron-mobility transistor (pHEMT) model for optimal drain efficiency. Large-signal model verification is undertaken where one-tone, load-pull, and wireless code-division multiple-access baseband time-domain tests are compared for simulated and experimental cases. Following a detailed theoretical analysis, a class-F matching network is proposed that suppresses the necessary load harmonics and delivers maximum drain efficiency. Utilizing the GaAs pHEMT model in computer-aided design, a microstrip matching network layout was generated and built at 2 GHz. The drain efficiency recorded for the first-pass effort was 70.5% with the use of no post-fabrication circuit tuning. Excellent agreement is also observed between the PAs simulated and measured performance, thus highlighting the advantages of an accurate device model in PA design.

In the framework of Power Amplifier (PA) design for communications, frequency domain non-linear behavioural models have shown their potential as efficient complementary modelling tools when Field Effect Transistor compact models are not available or sufficiently accurate. The Admittance behavioural model, formulated in the V-I domain, is especially suitable for device size and fundamental frequency scaling. It is important to note that the direct extraction of this model, from the Nonlinear Vector Network Analyser (NVNA) load-pull (LP) measurements, requires some extra processing since it necessitates a Look-up-Table indexed to |V11| rather than |A11|. When using such models in PA design, there is the need for the user to select the necessary model complexity. To address this requirement, in this paper, a systematic analysis methodology, to guide the user, is presented and validated in different PA design scenarios. The methodology was tested using NVNA LP measurements of GaN Heterostructure FETs. A fifth order Admittance model formulation showed good accuracy in the studied PA design scenarios.

SummaryAs wireless cellular communication keeps expanding toward higher bandwidth, multiband signals, and high frequencies of operation, the design of power efficient radio frequency power amplifiers (PAs) for cellular phone basestations is submitted to more stringent requirements. This paper discusses the promising technique of nonlinear embedding, which may help stream line the design of such PAs. To this order, the design of a GaN radio frequency PA from device modeling to circuit design is presented. The large signal modeling of GaN high‐electron‐mobility transistors including thermal and trapping memory effects is discussed first. The nonlinear embedding device model is then introduced using the concept of an anti‐circuit transfer network. This embedding device model is then applied to the design of a Chireix amplifier. New Chireix design equations are developed to work with the memoryless inner core of the embedding device model, and their validity is confirmed in circuit simulations. The Chireix amplifier is then designed using the multi‐harmonic impedance terminations predicted by the embedding device model for the package reference planes. Finally, the resulting Chireix amplifier is implemented in a circuit simulator with the original GaN high‐electron‐mobility transistors device model and verified in simulations to have a performance approaching that of the originally targeted Chireix at the current reference planes. These theoretical and simulation results demonstrate the potential of the nonlinear embedding PA design technique in the design of Chireix power amplifiers. Copyright © 2016 John Wiley & Sons, Ltd.

T31 paper presents a novel radio frequency (RF) power amplifier (PA) design technique based on Volterra Series analysis. This design technique is able to calculate the nonlinearity of the PA circuit. In Class-AB RF PA design, the best bias circuit for the balance between efficiency and linearity can be calculated by using this design technique. Consequently the period of PA's design and experiment can be shortened. A test die is fabricated and the measurement result verifies the effectiveness of this design technique.

This paper presents a comprehensive overview of Gallium nitride (GaN)-based power amplifier (PA) design for various frequency bands. GaN-based technology has emerged as a promising alternative to traditional silicon-based amplifiers due to its superior performance characteristics, which are discussed in this paper. This paper also discusses the key design parameters and challenges associated with PA design. Various design techniques and topologies for GaN power amplifiers are explored besides addressing theoretical considerations of PA design along with a complete systematic design procedure for L-Band amplifier using the wolfspeed large signal GaN HEMT model. To further demonstrate the useful methodology, the designs of S-band and C-band PAs are also presented. GaN-based devices are very promising candidates for high-power applications. It is widely used in various high-power applications including communication and radar.

A novel broadband transformer‐based CMOS power amplifier (PA) design method is studied in this article. To obtain a broadband PA, the parasitic parameters of the transformer are absorbed into the PAs load match and their impacts on bandwidth are studied. The fully‐integrated PA combined with an 8‐shaped transformer is implemented in 0.13 μm CMOS process with only 1.2 × 1.2 mm2 chip size and operates at Class AB mode. The single‐stage PA delivers 27.36 dBm output power with 27% efficiency and has 10.5 dB gain. It has 500 MHz bandwidth (1 dB degeneration) in the large and small signal measurements. IMD3 and IMD5 are also lower than −25 dBc at 19 dBm across the bandwidth. The spectrum of PA can meet the m‐WiMAX spectrum mask at 19 dBm average power level. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:422–425, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25731

This paper presents a power amplifier (PA) design to improve linearity by using a novel power cell compensating the main nonlinear sources from the power devices and to improve the overall efficiency by a dynamic DC biasing circuit. An over-voltage protection circuit to ease output mismatch induced problems is included in this PA design. As a case study, this power amplifier is implemented with InGaP/GaAs HBT operating at 1880 MHz. The CDMA standard is used to evaluate its linearity and efficiency. The P1dB is improved from 30 dBm to 32 dBm and the cumulated output current is much improved in a wide output power range. The ACPR and ALTR at 28 dBm output power level are improved by 5 dB and 12 dB with the novel PA respectively. The over-voltage protection circuit works well under output mismatch conditions.